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公开(公告)号：US20200136599A1
公开(公告)日：2020-04-30
申请号：US16591758
申请日：2019-10-03
申请人： NXP USA, Inc.
摘要： An electronic system includes a clock generation circuit to generate a clock signal; and a duty cycle monitoring circuit, DTC, to monitor a duty cycle of the generated clock signal. The DTC includes a differential signal generator circuit to generate an inverted and a non-inverted representation of the generated clock signal. An averaging circuit averages the non-inverted representation and the inverted representation of the generated clock signal. A comparison circuit includes at least a first comparator to compare the averaged non-inverted representation of the generated clock signal with a second respective reference voltage threshold and a second comparator configured to compare the averaged inverted representation with a first respective reference voltage threshold. A reference voltage generation circuit provides the first respective reference voltage threshold associated with the averaged inverted representation of the generated clock signal and provides the second respective reference voltage threshold associated with the non-inverted representation of the generated clock signal. A summing circuit is sums outputs of the first and second comparators and outputs a monitored duty cycle of the generated clock signal.
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公开(公告)号：US11320526B2
公开(公告)日：2022-05-03
申请号：US16447908
申请日：2019-06-20
申请人： NXP USA, Inc.
发明人： Didier Salle , Cristian Pavao Moreira , Dominique Delbecq , Olivier Doaré , Jean-Stephane Vigier , Birama Goumballa
摘要： A communication unit (300) is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit (362) configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (384); and transmit the modulated master-slave clock signal (384) to the at least one slave device. The at least one slave device comprises a demodulator circuit (364) configured to: receive and demodulate the modulated master-slave clock signal (384); and re-create therefrom the system clock signal (388, 385) and the frame start signal (390, 386).
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公开(公告)号：US11131763B2
公开(公告)日：2021-09-28
申请号：US16426638
申请日：2019-05-30
申请人： NXP USA, INC.
摘要： A fast chirp Phase Locked Loop with a phase preset includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A phase preset circuit connects to the digital controller and the filter. The phase preset circuit supplies a phase preset current during a start frequency time preceding the chirp phase. The phase preset current is proportional to a VCO gain of the VCO and inversely proportional to a chirp current during the chirp phase.
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公开(公告)号：US20200003883A1
公开(公告)日：2020-01-02
申请号：US16447962
申请日：2019-06-21
申请人： NXP USA, Inc.
发明人： Olivier Doaré , Didier Salle , Cristian Pavao Moreira , Julien Orlando , Jean-Stephane Vigier , Andres Barrilado Gonzalez
摘要： A communication unit (700) is described that includes a plurality of cascaded devices that comprise at least one master device (710) and at least one slave device (720, 723) configured in a master-slave arrangement. The at least one master device (710) and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a same re-created system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742). The at least one master device (710) comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (708), configured to output a system clock signal (782, 784); and a modulator circuit (762) coupled to the clock generation circuit and configured to receive and distribute the system clock signal (784). The at least one master device (710) and at least one slave device (720, 723) each comprise: a demodulator circuit (764, 765) configured to receive the distributed system clock signal (784) and re-create therefrom a synchronized system clock signal (788, 790) used by a respective ADC, (741, 742) of each of the the master device (710) and at least one slave device (720).
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公开(公告)号：US11131762B2
公开(公告)日：2021-09-28
申请号：US16426623
申请日：2019-05-30
申请人： NXP USA, INC.
摘要： A fast chirp Phase Locked Loop with a boosted return time includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A boost circuit connects to the digital controller and the filter. The boost circuit supplies a boost current during the return phase. The boost current is proportional to a return slope of the return phase and inversely proportional to a VCO gain of the VCO.
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6.发明申请公开(公告)号：US20200007309A1
公开(公告)日：2020-01-02
申请号：US16447947
申请日：2019-06-20
申请人： NXP USA, Inc.
摘要： A communication unit (400, 500) is described that includes a plurality of cascaded devices that comprise at least one master device and at least one slave device configured in a master-slave arrangement and configured to process at least one of: transmit signals, and receive signals. The at least one master device includes: a clock generation circuit configured to output a system clock signal; a modulator circuit (562) coupled to the clock generation circuit and configured to receive the system clock signal and a frame start signal and embed the frame start signal into the system clock signal to produce a modulated embedded master-slave clock signal (584); and transmit the modulated embedded master-slave clock signal (584) to the at least one slave device to synchronise the system clock signal and the frame start signal between the at least one master device (510) and at least one slave device (520).
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公开(公告)号：US20200003882A1
公开(公告)日：2020-01-02
申请号：US16447908
申请日：2019-06-20
申请人： NXP USA, Inc.
发明人： Didier Salle , Cristian Pavao Moreira , Dominique Delbecq , Olivier Doaré , Jean-Stephane Vigier , Birama Goumballa
摘要： A communication unit (300) is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit (362) configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (384); and transmit the modulated master-slave clock signal (384) to the at least one slave device. The at least one slave device comprises a demodulator circuit (364) configured to: receive and demodulate the modulated master-slave clock signal (384); and re-create therefrom the system clock signal (388, 385) and the frame start signal (390, 386).
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公开(公告)号：US11054513B2
公开(公告)日：2021-07-06
申请号：US16447962
申请日：2019-06-21
申请人： NXP USA, Inc.
发明人： Olivier Doaré , Didier Salle , Cristian Pavao Moreira , Julien Orlando , Jean-Stephane Vigier , Andres Barrilado Gonzalez
IPC分类号： G01S13/34 , G01S7/35 , G01S7/40 , G01S13/931
摘要： A communication unit (700) is described that includes a plurality of cascaded devices that comprise at least one master device (710) and at least one slave device (720, 723) configured in a master-slave arrangement. The at least one master device (710) and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a same re-created system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742). The at least one master device (710) comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (708), configured to output a system clock signal (782, 784); and a modulator circuit (762) coupled to the clock generation circuit and configured to receive and distribute the system clock signal (784). The at least one master device (710) and at least one slave device (720, 723) each comprise: a demodulator circuit (764, 765) configured to receive the distributed system clock signal (784) and re-create therefrom a synchronized system clock signal (788, 790) used by a respective ADC, (741, 742) of each of the the master device (710) and at least one slave device (720).
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公开(公告)号：US10700672B2
公开(公告)日：2020-06-30
申请号：US16591758
申请日：2019-10-03
申请人： NXP USA, Inc.
摘要： An electronic system includes a clock generation circuit to generate a clock signal; and a duty cycle monitoring circuit, DTC, to monitor a duty cycle of the generated clock signal. The DTC includes a differential signal generator circuit to generate an inverted and a non-inverted representation of the generated clock signal. An averaging circuit averages the non-inverted representation and the inverted representation of the generated clock signal. A comparison circuit includes at least a first comparator to compare the averaged non-inverted representation of the generated clock signal with a second respective reference voltage threshold and a second comparator configured to compare the averaged inverted representation with a first respective reference voltage threshold. A reference voltage generation circuit provides the first respective reference voltage threshold associated with the averaged inverted representation of the generated clock signal and provides the second respective reference voltage threshold associated with the non-inverted representation of the generated clock signal. A summing circuit is sums outputs of the first and second comparators and outputs a monitored duty cycle of the generated clock signal.
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公开(公告)号：US20200057140A1
公开(公告)日：2020-02-20
申请号：US15999181
申请日：2018-08-17
申请人： NXP USA, Inc.
摘要： A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a phase-locked loop (PLL) frequency sampling circuit and a frequency sweep linearity measuring circuit. The PLL frequency sampling circuit comprises a frequency divider circuit for receiving a PLL output signal from a PLL and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.
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