Invention Grant
- Patent Title: Integrated tensile strained silicon NFET and compressive strained silicon-germanium PFET implemented in FinFET technology
-
Application No.: US16180223Application Date: 2018-11-05
-
Publication No.: US11133331B2Publication Date: 2021-09-28
- Inventor: Qing Liu , Pierre Morin
- Applicant: STMicroelectronics, Inc.
- Applicant Address: US TX Coppell
- Assignee: STMicroelectronics, Inc.
- Current Assignee: STMicroelectronics, Inc.
- Current Assignee Address: US TX Coppell
- Agency: Crowe & Dunlevy
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L27/12 ; H01L21/8238 ; H01L21/308 ; H01L21/02 ; H01L21/3105 ; H01L21/324 ; H01L27/092 ; H01L21/84 ; H01L29/10 ; H01L29/66 ; H01L29/78

Abstract:
A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).
Public/Granted literature
Information query
IPC分类: