Invention Grant
- Patent Title: Clocking synchronization method and apparatus
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Application No.: US16430170Application Date: 2019-06-03
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Publication No.: US11144088B2Publication Date: 2021-10-12
- Inventor: Jagannadha Rao V. V. V. Rapeta , Mikal Hunsaker , Ronald Swartz , Robert Fulton , L. Mark Elzinga , Young Min Park , David R. Mulvihill
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: G06F1/12
- IPC: G06F1/12 ; G06F13/42

Abstract:
Method and apparatus associated with clocking synchronization are disclosed herein. In various embodiment, a method for communication comprises: entering a clock training period, on successful performance of clock training handshake; entering a start static phase measurement (SSPM) sequence of clock training period, receiving a recovered clock; and processing the recovered clock to determine parts-per-million (PPM) differences, to be subsequently applied to compensate for the PPM differences determined during subsequent clocking synchronization. Linking training is performed after the subsequent clocking synchronization. In various embodiments, clocking synchronization comprises SSC synchronization. Other embodiments are also described and claimed.
Public/Granted literature
- US20190332139A1 Clocking Synchronization Method and Apparatus Public/Granted day:2019-10-31
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