Invention Grant
- Patent Title: Method for forming and patterning a layer and/or substrate
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Application No.: US16853500Application Date: 2020-04-20
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Publication No.: US11145509B2Publication Date: 2021-10-12
- Inventor: Takehito Koshizawa , Rui Cheng , Tejinder Singh , Hidetaka Oshio
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L21/311 ; H01L21/3213 ; H01L21/768

Abstract:
In an embodiment, a method for forming features for semiconductor processing. A first mandrel and a second mandrel are formed on a substrate. A first spacer is formed along a first sidewall of the first mandrel, and a second spacer is formed along a second sidewall of the second mandrel. A gap is defined between the first spacer and the second spacer. The gap is filled by a gap-filling material. In some examples, the gap-filling material includes a doped silicon material. In some examples, the first spacer and the second spacer each include a doped silicon material.
Public/Granted literature
- US20200373159A1 METHOD FOR FORMING AND PATTERNING A LAYER AND/OR SUBSTRATE Public/Granted day:2020-11-26
Information query
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