Invention Grant
- Patent Title: Technologies for filtering memory access transactions received from one or more I/O devices
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Application No.: US16234871Application Date: 2018-12-28
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Publication No.: US11163913B2Publication Date: 2021-11-02
- Inventor: Luis Kida , Krystof Zmudzinski , Reshma Lal , Pradeep Pappachan , Abhishek Basak , Anna Trikalinou
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- Main IPC: G06F21/78
- IPC: G06F21/78 ; G06F21/44 ; G06F21/85

Abstract:
Technologies for secure I/O include a compute device having a processor, a memory, an input/output (I/O) device, and a filter logic. The filter logic is configured to receive a first key identifier from the processor, wherein the first key identifier is indicative of a shared memory range includes a shared key identifier range to be used for untrusted I/O devices and receive a transaction from the I/O device, wherein the transaction includes a second key identifier and a trust device ID indicator associated with the I/O device. The filter logic is further configured to determine whether the transaction is asserted with the trust device ID indicator indicative of whether the I/O device is assigned to a trust domain and determine, in response to a determination that the transaction is not asserted with the trust device ID indicator, whether the second key identifier matches the first key identifier.
Public/Granted literature
- US11373013B2 Technologies for filtering memory access transactions received from one or more I/O devices Public/Granted day:2022-06-28
Information query