Disaggregated computing for distributed confidential computing environment

    公开(公告)号:US12033005B2

    公开(公告)日:2024-07-09

    申请号:US17532562

    申请日:2021-11-22

    申请人: Intel Corporation

    摘要: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes a programmable integrated circuit (IC) comprising secure device manager (SDM) hardware circuitry to: receive a tenant bitstream of a tenant and a tenant use policy for utilization of the programmable IC via the tenant bitstream, wherein the tenant use policy is cryptographically bound to the tenant bitstream by a cloud service provider (CSP) authorizing entity and signed with a signature of the CSP authorizing entity; in response to successfully verifying the signature, extract the tenant use policy to provide to a policy manager of the programmable IC for verification; in response to the policy manager verifying the tenant bitstream based on the tenant use policy, configure a partial reconfiguration (PR) region of the programmable IC using the tenant bitstream; and associate a slot ID of the PR region with the tenant use policy.

    SECURE DATA OFFLOAD IN A DISAGGREGATED AND HETEROGENOUS ORCHESTRATION ENVIRONMENT

    公开(公告)号:US20240220639A1

    公开(公告)日:2024-07-04

    申请号:US18148576

    申请日:2022-12-30

    申请人: Intel Corporation

    IPC分类号: G06F21/60 G06F21/57 G06F21/85

    摘要: An apparatus comprises a compute complex comprising one or more processing resources to execute a software process, a hardware processor to initiate an authentication request to at least one adjunct processing hardware device communicatively coupled to the compute complex, establish a session key with the at least one adjunct processing hardware device, negotiate, with a hypervisor, a virtual function allocation for at least one virtual adjunct processing device to be implemented by the at least one adjunct processing hardware device to define a configuration in a trusted page table, verify the configuration with the at least one adjunct processing hardware device using the session key, and lock the configuration in the trusted table.

    INTEGRITY PROTECTED COMMAND BUFFER EXECUTION

    公开(公告)号:US20240121097A1

    公开(公告)日:2024-04-11

    申请号:US18391375

    申请日:2023-12-20

    申请人: Intel Corporation

    IPC分类号: H04L9/32 G06F21/60 H04L9/08

    摘要: Embodiments are directed to providing integrity-protected command buffer execution. An embodiment of an apparatus includes a computer-readable memory comprising one or more command buffers and a processing device communicatively coupled to the computer-readable memory to read, from a command buffer of the computer-readable memory, a first command received from a host device, the first command executable by one or more processing elements on the processing device, the first command comprising an instruction and associated parameter data, compute a first authentication tag using a cryptographic key associated with the host device, the instruction and at least a portion of the parameter data, and authenticate the first command by comparing the first authentication tag with a second authentication tag computed by the host device and associated with the command.

    In-place memory copy during remote data transfer in heterogeneous compute environment

    公开(公告)号:US11947801B2

    公开(公告)日:2024-04-02

    申请号:US17876936

    申请日:2022-07-29

    申请人: Intel Corporation

    摘要: An apparatus to facilitate in-place memory copy during remote data transfer in a heterogeneous compute environment is disclosed. The apparatus includes a processor to receive data via a network interface card (NIC) of a hardware accelerator device; identify a destination address of memory of the hardware accelerator device to write the data; determine that access control bits of the destination address in page tables maintained by a memory management unit (MMU) indicate that memory pages of the destination address are both registered and free; write the data to the memory pages of the destination address; and update the access control bits for memory pages of the destination address to indicate that the memory pages are restricted, wherein setting the access control bits to restricted prevents the NIC and a compute kernel of the hardware accelerator device from accessing the memory pages.

    ISOLATION OF MEMORY REGIONS IN TRUSTED DOMAIN

    公开(公告)号:US20240070091A1

    公开(公告)日:2024-02-29

    申请号:US17822847

    申请日:2022-08-29

    申请人: Intel Corporation

    IPC分类号: G06F12/14

    摘要: An apparatus comprises a hardware processor to program a memory table for a trusted domain with a first device identifier associated with a device, a guest physical address (GPA) range associated with the device, and a guest physical address offset, receive a memory access request from the device, the memory access request comprising a second device identifier and a guest physical address, and validate the memory access request using the memory table.

    IN-PLACE MEMORY COPY DURING REMOTE DATA TRANSFER IN HETEROGENEOUS COMPUTE ENVIRONMENT

    公开(公告)号:US20240036733A1

    公开(公告)日:2024-02-01

    申请号:US17876936

    申请日:2022-07-29

    申请人: Intel Corporation

    IPC分类号: G06F3/06

    摘要: An apparatus to facilitate in-place memory copy during remote data transfer in a heterogeneous compute environment is disclosed. The apparatus includes a processor to receive data via a network interface card (NIC) of a hardware accelerator device; identify a destination address of memory of the hardware accelerator device to write the data; determine that access control bits of the destination address in page tables maintained by a memory management unit (MMU) indicate that memory pages of the destination address are both registered and free; write the data to the memory pages of the destination address; and update the access control bits for memory pages of the destination address to indicate that the memory pages are restricted, wherein setting the access control bits to restricted prevents the NIC and a compute kernel of the hardware accelerator device from accessing the memory pages.