Invention Grant
- Patent Title: Etch damage and ESL free dual damascene metal interconnect
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Application No.: US16426074Application Date: 2019-05-30
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Publication No.: US11171041B2Publication Date: 2021-11-09
- Inventor: Sunil Kumar Singh , Chung-Ju Lee , Tien-I Bao
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/768 ; H01L23/522 ; H01L23/532 ; H01L23/48

Abstract:
Some embodiments relate to a semiconductor device manufacturing process. In the process, a substrate is provided, and a sacrificial layer is formed over the substrate. An opening is patterned through the sacrificial layer, and the opening is filled with conductive material. The sacrificial layer is removed while the conductive material is left in place. A first dielectric layer is formed along sidewalls of the conductive material that was left in place.
Public/Granted literature
- US20190279896A1 ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT Public/Granted day:2019-09-12
Information query
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