Invention Grant
- Patent Title: Semiconductor memory device including work function adjusting layer in buried gate line and method of manufacturing the same
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Application No.: US15966554Application Date: 2018-04-30
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Publication No.: US11189618B2Publication Date: 2021-11-30
- Inventor: Namho Jeon , Jin-Seong Lee , Hyun-jung Lee , Dongsoo Woo , Donggyu Heo , Jaeho Hong
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Agency: F. Chau & Associates, LLC
- Priority: KR10-2017-0134232 20171016
- Main IPC: H01L27/105
- IPC: H01L27/105 ; H01L29/06 ; H01L21/8238 ; H01L21/8239 ; H01L27/108

Abstract:
Disclosed are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a device isolation layer defining active regions of a substrate, and gate lines buried in the substrate and extending across the active regions. Each of the gate lines includes a conductive layer, a liner layer disposed between and separating the conductive layer and the substrate, and a first work function adjusting layer disposed on the conductive layer and the liner layer. The first work function adjusting layer includes a first work function adjusting material. A work function of the first work function adjusting layer is less than those of the conductive layer and the liner layer.
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Information query
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