Invention Grant
- Patent Title: Thin-film transistors with low contact resistance
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Application No.: US16647679Application Date: 2018-01-10
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Publication No.: US11189733B2Publication Date: 2021-11-30
- Inventor: Abhishek A. Sharma , Van H. Le , Li Huey Tan , Tristan A. Tronic , Benjamin Chu-Kung , Jack T. Kavalieros , Tahir Ghani
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- International Application: PCT/US2018/013181 WO 20180110
- International Announcement: WO2019/139577 WO 20190718
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L29/06 ; H01L29/20 ; H01L29/423 ; H01L29/66

Abstract:
Techniques are disclosed for forming thin-film transistors (TFTs) with low contact resistance. As disclosed in the present application, the low contact resistance can be achieved by intentionally thinning one or both of the source/drain (S/D) regions of the thin-film layer of the TFT device. As the TFT layer may have an initial thickness in the range of 20-65 nm, the techniques for thinning the S/D regions of the TFT layer described herein may reduce the thickness in one or both of those S/D regions to a resulting thickness of 3-10 nm, for example. Intentionally thinning one or both of the S/D regions of the TFT layer induces more electrostatic charges inside the thinned S/D region, thereby increasing the effective dopant in that S/D region. The increase in effective dopant in the thinned S/D region helps lower the related contact resistance, thereby leading to enhanced overall device performance.
Public/Granted literature
- US20200235246A1 THIN-FILM TRANSISTORS WITH LOW CONTACT RESISTANCE Public/Granted day:2020-07-23
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