公开(公告)号：US11862728B2

公开(公告)日：2024-01-02

申请号：US17492487

申请日：2021-10-01

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Shriram Shivaraman ,  Benjamin Chu-Kung ,  Yih Wang ,  Tahir Ghani

IPC分类号： H01L29/786 ,  H01L29/08 ,  H01L29/04 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L29/423 ,  H10B12/00 ,  H01L21/311

CPC分类号： H01L29/78642 ,  H01L21/02647 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42384 ,  H01L29/6656 ,  H01L29/6675 ,  H01L29/78648 ,  H01L29/78696 ,  H10B12/05 ,  H10B12/315 ,  H10B12/50 ,  H01L21/31116 ,  H01L29/66969 ,  H01L29/7869

摘要： Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.

公开(公告)号：US11862715B2

公开(公告)日：2024-01-02

申请号：US17745822

申请日：2022-05-16

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Willy Rachmady ,  Uygar Avci ,  Ashish Agrawal ,  Benjamin Chu-Kung

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786

CPC分类号： H01L29/66977 ,  H01L29/0649 ,  H01L29/41733 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696

摘要： Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

公开(公告)号：US11699756B2

公开(公告)日：2023-07-11

申请号：US17541199

申请日：2021-12-02

申请人： Intel Corporation

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC分类号： H01L29/78 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/7846 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/42364

摘要： Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.

公开(公告)号：US11690215B2

公开(公告)日：2023-06-27

申请号：US15943576

申请日：2018-04-02

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Yih Wang ,  Benjamin Chu-Kung ,  Shriram Shivaraman

IPC分类号： H10B12/00

CPC分类号： H10B12/34 ,  H10B12/03 ,  H10B12/36 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488

摘要： A method is described. The method includes forming bit line structures above bitline contact structures, forming a first material on top surfaces and sidewall surfaces of the bit line structures to establish step structures for via formation, and forming a second material on the top surface of the first material. Capacitor landing structures are formed by patterning the second material.

公开(公告)号：US11658222B2

公开(公告)日：2023-05-23

申请号：US16633603

申请日：2017-09-27

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey ,  Shriram Shivaraman ,  Sean T. Ma ,  Benjamin Chu-Kung

IPC分类号： H01L29/423 ,  H01L29/40 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/4234 ,  H01L29/40117 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/786

摘要： An embodiment includes an apparatus comprising: a substrate; a thin film transistor (TFT) comprising: source, drain, and gate contacts; a semiconductor material, comprising a channel, between the substrate and the gate contact; a gate dielectric layer between the gate contact and the channel; and an additional layer between the channel and the substrate; wherein (a)(i) the channel includes carriers selected from the group consisting of hole carriers or electron carriers, (a)(ii) the additional layer includes an insulator material that includes charged particles having a polarity equal to a polarity of the carriers. Other embodiments are described herein.

公开(公告)号：US11575005B2

公开(公告)日：2023-02-07

申请号：US15942252

申请日：2018-03-30

申请人： INTEL CORPORATION

发明人： Seung Hoon Sung ,  Dipanjan Basu ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Siddharth Chouksey ,  Cory C. Bomberger ,  Tahir Ghani ,  Anand S. Murthy ,  Jack T. Kavalieros

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16

摘要： An integrated circuit structure includes: a semiconductor nanowire extending in a length direction and including a body portion; a gate dielectric surrounding the body portion; a gate electrode insulated from the body portion by the gate dielectric; a semiconductor source portion adjacent to a first side of the body portion; and a semiconductor drain portion adjacent to a second side of the body portion opposite the first side, the narrowest dimension of the second side of the body portion being smaller than the narrowest dimension of the first side. In an embodiment, the nanowire has a conical tapering. In an embodiment, the gate electrode extends along the body portion in the length direction to the source portion, but not to the drain portion. In an embodiment, the drain portion at the second side of the body portion has a lower dopant concentration than the source portion at the first side.

公开(公告)号：US11335793B2

公开(公告)日：2022-05-17

申请号：US16957667

申请日：2018-02-28

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Willy Rachmady ,  Uygar Avci ,  Ashish Agrawal ,  Benjamin Chu-Kung

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786

摘要： Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

公开(公告)号：US11189733B2

公开(公告)日：2021-11-30

申请号：US16647679

申请日：2018-01-10

申请人： INTEL CORPORATION

发明人： Abhishek A. Sharma ,  Van H. Le ,  Li Huey Tan ,  Tristan A. Tronic ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Tahir Ghani

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66

摘要： Techniques are disclosed for forming thin-film transistors (TFTs) with low contact resistance. As disclosed in the present application, the low contact resistance can be achieved by intentionally thinning one or both of the source/drain (S/D) regions of the thin-film layer of the TFT device. As the TFT layer may have an initial thickness in the range of 20-65 nm, the techniques for thinning the S/D regions of the TFT layer described herein may reduce the thickness in one or both of those S/D regions to a resulting thickness of 3-10 nm, for example. Intentionally thinning one or both of the S/D regions of the TFT layer induces more electrostatic charges inside the thinned S/D region, thereby increasing the effective dopant in that S/D region. The increase in effective dopant in the thinned S/D region helps lower the related contact resistance, thereby leading to enhanced overall device performance.

公开(公告)号：US11101350B2

公开(公告)日：2021-08-24

申请号：US15930627

申请日：2020-05-13

申请人： INTEL CORPORATION

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Jack T. Kavalieros ,  Tahir Ghani ,  Harold W. Kennel

IPC分类号： H01L27/00 ,  H01L29/00 ,  H01L29/10 ,  H01L21/02 ,  H01L21/22 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

摘要： Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements. The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (e.g., B, P, or As) into the adjacent Ge-rich channel region. In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon. Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion. In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region. Numerous embodiments, configurations, and variations will be apparent.

公开(公告)号：US11004954B2

公开(公告)日：2021-05-11

申请号：US16326844

申请日：2016-09-30

申请人： INTEL CORPORATION

发明人： Karthik Jambunathan ,  Glenn A. Glass ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Seung Hoon Sung ,  Benjamin Chu-Kung ,  Tahir Ghani

IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786 ,  H01L29/775 ,  H01L29/06 ,  B82Y10/00

摘要： Integrated circuit transistor structures are disclosed that include a single crystal buffer structure that is lattice matched to the underlying single crystal silicon substrate. The buffer structure may be used to reduce sub-fin leakage in non-planar transistors, but can also be used in planar configurations. In some embodiments, the buffer structure is a single continuous layer of high bandgap dielectric material that is lattice matched to silicon. The techniques below can be utilized on NMOS and PMOS transistors, including any number of group IV and III-V semiconductor channel materials.