Invention Grant
- Patent Title: Reducing in-plane distortion from wafer to wafer bonding using a dummy wafer
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Application No.: US15943551Application Date: 2018-04-02
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Publication No.: US11195719B2Publication Date: 2021-12-07
- Inventor: Chytra Pawashe , Daniel Pantuso
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L21/18
- IPC: H01L21/18 ; H01L21/20

Abstract:
Embodiments of the present disclosure describe techniques for reducing in-plane distortion from wafer to wafer bonding using a dummy wafer. One embodiment is an apparatus formed using a dummy wafer, the apparatus comprising: a device layer fusion bonded to a first side of a carrier wafer, wherein the dummy wafer comprises a first wafer and the carrier wafer comprises a second wafer that is different than the first wafer; wherein the device layer comprise a portion of a third wafer that is different than the second wafer; and wherein a second opposite side of the carrier wafer includes: a removal process artifact, wherein a distortion signature present in the portion of the second wafer is indicative of the use of the dummy wafer fusion bonded to the second side of the carrier wafer, or a remainder of the dummy wafer. Other embodiments may be disclosed and/or claimed.
Public/Granted literature
- US20190304784A1 REDUCING IN-PLANE DISTORTION FROM WAFER TO WAFER BONDING USING A DUMMY WAFER Public/Granted day:2019-10-03
Information query
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