公开(公告)号：US10707186B1

公开(公告)日：2020-07-07

申请号：US16125261

申请日：2018-09-07

申请人： Intel Corporation

发明人： Mauro J. Kobrinsky ,  Jasmeet S. Chawla ,  Stefan Meister ,  Myra McDonnell ,  Chytra Pawashe ,  Daniel Pantuso

IPC分类号： B32B37/02 ,  H01L23/00

摘要： Techniques and mechanisms for forming a bond between wafers using a compliant layer. In an embodiment, a layer or layers of one or more compliant materials is provided on a first surface of a first wafer, and the one or more compliant layers are subsequently bonded to a second surface of a second wafer. The bonded wafers are heated to an elevated temperature at which a compliant layer exhibits non-elastic deformations to facilitate relaxation of stresses caused by wafer distortions. In another embodiment, a material of the compliant layer exhibits viscoelastic behavior at room temperature, wherein stress is mitigated by allowing wafer distortion to relax at room temperature.

公开(公告)号：US11195719B2

公开(公告)日：2021-12-07

申请号：US15943551

申请日：2018-04-02

申请人： Intel Corporation

发明人： Chytra Pawashe ,  Daniel Pantuso

IPC分类号： H01L21/18 ,  H01L21/20

摘要： Embodiments of the present disclosure describe techniques for reducing in-plane distortion from wafer to wafer bonding using a dummy wafer. One embodiment is an apparatus formed using a dummy wafer, the apparatus comprising: a device layer fusion bonded to a first side of a carrier wafer, wherein the dummy wafer comprises a first wafer and the carrier wafer comprises a second wafer that is different than the first wafer; wherein the device layer comprise a portion of a third wafer that is different than the second wafer; and wherein a second opposite side of the carrier wafer includes: a removal process artifact, wherein a distortion signature present in the portion of the second wafer is indicative of the use of the dummy wafer fusion bonded to the second side of the carrier wafer, or a remainder of the dummy wafer. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US10720345B1

公开(公告)日：2020-07-21

申请号：US16125248

申请日：2018-09-07

申请人： Intel Corporation

发明人： Mauro J. Kobrinsky ,  Myra McDonnell ,  Brennen K. Mueller ,  Chytra Pawashe ,  Daniel Pantuso ,  Paul B. Fischer ,  Lance C. Hibbeler ,  Martin Weiss

IPC分类号： H01L21/30 ,  H01L21/67

摘要： Techniques and mechanisms for forming a bond between two wafers. In an embodiment, a first wafer and a second wafer are positioned with respective wafer holders, and are deformed to form a first deformation of the first wafer and a second deformation of the second wafer. The first deformation and the second deformation are symmetrical with respect to a centerline which is between the first wafer and the second wafer. A portion of the first deformation is made to contact, and form a bond with, another portion of the second deformation. The bond is propagated along respective surfaces of the wafers to form a coupling therebetween. In another embodiment, one of the wafer holders comprises one of an array of elements to locally heat or cool a wafer, or an array of displacement stages to locally deform said wafer.

公开(公告)号：US09947805B2

公开(公告)日：2018-04-17

申请号：US15151381

申请日：2016-05-10

申请人： Intel Corporation

发明人： Chytra Pawashe ,  Kevin Lin ,  Anurag Chaudhry ,  Raseong Kim ,  Seiyon Kim ,  Kelin Kuhn ,  Sasikanth Manipatruni ,  Rafael Rios ,  Ian A. Young

IPC分类号： H01H51/22 ,  H01L29/84 ,  H01H59/00 ,  B82Y10/00 ,  H01H1/00 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161 ,  H01H9/02

CPC分类号： H01L29/84 ,  B82Y10/00 ,  H01H1/0094 ,  H01H9/0271 ,  H01H59/0009 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/161

摘要： Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.

公开(公告)号：US11721554B2

公开(公告)日：2023-08-08

申请号：US16356402

申请日：2019-03-18

申请人： Intel Corporation

发明人： Anant Jahagirdar ,  Chytra Pawashe ,  Aaron Lilak ,  Myra McDonnell ,  Brennen Mueller ,  Mauro Kobrinsky

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/161 ,  H01L21/20 ,  H01L21/56 ,  H01L21/02 ,  H01L21/603

CPC分类号： H01L21/2007 ,  H01L21/0226 ,  H01L21/56 ,  H01L21/603

摘要： Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.

公开(公告)号：US10282965B2

公开(公告)日：2019-05-07

申请号：US14567625

申请日：2014-12-11

申请人： Intel Corporation

发明人： Jessica Gullbrand ,  Melissa A. Cowan ,  Chytra Pawashe ,  Feras Eid

IPC分类号： G01N1/22 ,  F15D1/00 ,  G08B21/18 ,  H01L23/473 ,  G08B25/08 ,  G08B21/12 ,  G01N1/24

摘要： Techniques are disclosed for using synthetic jet technology as an air delivery device for sensing applications. In particular, a synthetic jet device is used to deliver a controlled airflow or other fluidic flow to a sensor measurement area. Such a sensing system can be used to detect accurate concentration of target features present in the ambient surroundings, such as gases, particles, solutions, mixtures, and any other environmental features that can be sensed from a controlled airflow. An example application is air quality monitoring by using one or more synthetic jet devices to deliver a known or otherwise controlled airflow to a sensing area, thereby allowing for detection of harmful or otherwise unacceptable concentrations of particulate matter, gases, or air pollutants. In some embodiments, a synthetic jet device is operatively coupled with a sensor via a flow channel in a common housing, so as to provide a controlled flow sensing system.

公开(公告)号：US10242892B2

公开(公告)日：2019-03-26

申请号：US15512342

申请日：2014-10-17

申请人： Intel Corporation

发明人： Peter L. Chang ,  Chytra Pawashe ,  Michael C. Mayberry ,  Jia-Hung Tseng

IPC分类号： H01L21/67 ,  H01L23/00 ,  H01L21/683 ,  H01L25/075 ,  H01L33/00 ,  H01L33/36 ,  H01L33/44 ,  H01L33/62

摘要： Micro pick-and-bond heads, assembly methods, and device assemblies. In, embodiments, micro pick-and-bond heads transfer micro device elements, such as (micro) LEDs, en masse from a source substrate to a target substrate, such as a LED display substrate. Anchor and release structures on the source substrate enable device elements to be separated from a source substrate, while pressure sensitive adhesive (PSA) enables device elements to be temporarily affixed to pedestals of a micro pick-and-bond head. Once the device elements are permanently affixed to a target substrate, the PSA interface may be defeated through peeling and/or thermal decomposition of an interface layer.

公开(公告)号：US10204808B2

公开(公告)日：2019-02-12

申请号：US15512342

申请日：2014-10-17

申请人： Intel Corporation

发明人： Peter L. Chang ,  Chytra Pawashe ,  Michael C. Mayberry ,  Jia-Hung Tseng

IPC分类号： H01L21/67 ,  H01L23/00 ,  H01L21/683 ,  H01L25/075 ,  H01L33/00 ,  H01L33/36 ,  H01L33/44 ,  H01L33/62

摘要： Micro pick-and-bond heads, assembly methods, and device assemblies. In, embodiments, micro pick-and-bond heads transfer micro device elements, such as (micro) LEDs, en masse from a source substrate to a target substrate, such as a LED display substrate. Anchor and release structures on the source substrate enable device elements to be separated from a source substrate, while pressure sensitive adhesive (PSA) enables device elements to be temporarily affixed to pedestals of a micro pick-and-bond head. Once the device elements are permanently affixed to a target substrate, the PSA interface may be defeated through peeling and/or thermal decomposition of an interface layer.

公开(公告)号：US20220415807A1

公开(公告)日：2022-12-29

申请号：US17358971

申请日：2021-06-25

申请人： Intel Corporation

发明人： Chytra Pawashe ,  Lei Jiang ,  Colin Landon ,  Daniel Pantuso ,  Edwin Ramayya ,  Jeffrey Hicks ,  Mehmet Koker Aykol

IPC分类号： H01L23/538 ,  H01L23/36

摘要： A device structure includes a first interconnect layer, a second interconnect layer, a device layer including a comprising a plurality of devices, where the device layer is between the first interconnect layer and the second interconnect layer. The device structure further includes a dielectric layer adjacent the second interconnect layer, where the dielectric layer includes one or more of metallic dopants or a plurality of metal structures, wherein the plurality of metal structures is electrically isolated from interconnect structures but in contact with a dielectric material of the second interconnect layer, and where the individual ones of the plurality of metal structures is above a region including at least some of the plurality of devices. The device structure further includes a substrate adjacent to the dielectric layer and a heat sink coupled with the substrate.

公开(公告)号：US09926193B2

公开(公告)日：2018-03-27

申请号：US15301337

申请日：2014-06-27

申请人： Intel Corporation

发明人： Jorge A. Munoz ,  Dmitri E. Nikonov ,  Kelin J. Kuhn ,  Patrick Theofanis ,  Chytra Pawashe ,  Kevin Lin ,  Seiyon Kim

IPC分类号： B82B1/00 ,  B82B3/00 ,  H01L29/66 ,  H01L29/84 ,  H01L29/82 ,  H01H59/00 ,  B82Y15/00 ,  B82Y25/00 ,  B82Y40/00

CPC分类号： B82B1/005 ,  B81B3/0016 ,  B81B7/02 ,  B81B2201/014 ,  B81B2203/0118 ,  B82B1/002 ,  B82B3/0023 ,  B82Y15/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01H1/0094 ,  H01H1/54 ,  H01H59/0009 ,  H01L29/66227 ,  H01L29/82 ,  H01L29/84 ,  Y10S977/732 ,  Y10S977/838 ,  Y10S977/888 ,  Y10S977/938

摘要： Nanoelectromechanical (NEMS) devices having nanomagnets for an improved range of operating voltages and improved control of dimensions of a cantilever are described. For example, in an embodiment, a nanoelectromechanical (NEMS) device includes a substrate layer, a first magnetic layer disposed above the substrate layer, a first dielectric layer disposed above the first magnetic layer, a second dielectric disposed above the first dielectric layer, and a cantilever disposed above the second dielectric layer. The cantilever bends from a first position to a second position towards the substrate layer when a voltage is applied to the cantilever.