- Patent Title: Implementing a JTAG device chain in multi-die integrated circuit
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Application No.: US16841564Application Date: 2020-04-06
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Publication No.: US11199582B2Publication Date: 2021-12-14
- Inventor: Roger D. Flateau, Jr. , Srinu Sunkara
- Applicant: XILINX, INC.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G06F9/30 ; G01R31/317 ; G08G1/0968

Abstract:
An example integrated circuit (IC) die in a multi-die IC package, the multi-die IC package having a test access port (TAP) comprising a test data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS), is described. The IC die includes a Joint Test Action Group (JTAG) controller having a JTAG interface that includes a TDI, a TDO, a TCK, and a TMS, a first output coupled to first routing in the multi-die IC package, a first input coupled to the first routing or to second routing in the multi-die IC package, a master return path coupled to the first input, and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller, and selectively couple, in response to a first control signal, the TDO of the TAP to either the master return path or the TDO of the JTAG controller.
Public/Granted literature
- US20210311115A1 IMPLEMENTING A JTAG DEVICE CHAIN IN MULTI-DIE INTEGRATED CIRCUIT Public/Granted day:2021-10-07
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