公开(公告)号：US11675006B2

公开(公告)日：2023-06-13

申请号：US17644067

申请日：2021-12-13

Applicant: XILINX, INC.

Inventor： Roger D. Flateau, Jr. ,  Srinu Sunkara

IPC: G01R31/3177 ,  G01R31/317 ,  G06F9/30 ,  G08G1/0968

CPC classification number: G01R31/3177 ,  G01R31/31701 ,  G01R31/31712 ,  G01R31/31727 ,  G06F9/30145 ,  G08G1/096805 ,  G08G1/096811 ,  G08G1/096816 ,  G08G1/096822

Abstract: An example integrated circuit (IC) die in a multi-die IC package, the multi-die IC package having a test access port (TAP) comprising a test data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS), is described. The IC die includes a Joint Test Action Group (JTAG) controller having a JTAG interface that includes a TDI, a TDO, a TCK, and a TMS, a first output coupled to first routing in the multi-die IC package, a first input coupled to the first routing or to second routing in the multi-die IC package, a master return path coupled to the first input, and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller, and selectively couple, in response to a first control signal, the TDO of the TAP to either the master return path or the TDO.

公开(公告)号：US11199582B2

公开(公告)日：2021-12-14

申请号：US16841564

申请日：2020-04-06

Applicant: XILINX, INC.

Inventor： Roger D. Flateau, Jr. ,  Srinu Sunkara

IPC: G01R31/3177 ,  G06F9/30 ,  G01R31/317 ,  G08G1/0968

Abstract: An example integrated circuit (IC) die in a multi-die IC package, the multi-die IC package having a test access port (TAP) comprising a test data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS), is described. The IC die includes a Joint Test Action Group (JTAG) controller having a JTAG interface that includes a TDI, a TDO, a TCK, and a TMS, a first output coupled to first routing in the multi-die IC package, a first input coupled to the first routing or to second routing in the multi-die IC package, a master return path coupled to the first input, and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller, and selectively couple, in response to a first control signal, the TDO of the TAP to either the master return path or the TDO of the JTAG controller.