Invention Grant
- Patent Title: Structure for arrayed partial molding of packages
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Application No.: US16687778Application Date: 2019-11-19
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Publication No.: US11211263B2Publication Date: 2021-12-28
- Inventor: Srikanth Kulkarni , Rajneesh Kumar , Sayok Chattopadhyay
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Patterson & Sheridan, L.L.P.
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/31 ; H01L25/16 ; H01L21/768 ; H01L21/66 ; H01L21/78

Abstract:
Certain aspects of the present disclosure provide apparatus and techniques for partially molding packages for integrated circuits. A packaged assembly for integrated circuits includes: a substrate having at least one mold barrier between a first region on a first surface of the substrate and a second region on the first surface; a die attached to the substrate; one or more components attached to the substrate in the first region; and a first encapsulant over the one or more components in the first region, wherein the at least one mold barrier is configured to block a portion of the first encapsulant from moving from the first region of the substrate to the second region of the substrate during an application of the first encapsulant.
Public/Granted literature
- US20210151330A1 STRUCTURE FOR ARRAYED PARTIAL MOLDING OF PACKAGES Public/Granted day:2021-05-20
Information query
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