公开(公告)号：US10510733B2

公开(公告)日：2019-12-17

申请号：US16185635

申请日：2018-11-09

Applicant: QUALCOMM Incorporated

Inventor： Rajneesh Kumar ,  Chin-Kwan Kim ,  Milind Shah

IPC: H01L25/10 ,  H01L23/552 ,  H01L23/66 ,  H01L25/065 ,  H04W4/80 ,  H01L25/00 ,  H04W4/00 ,  H01L23/00 ,  H01L25/16 ,  H01L21/56

Abstract: A device that includes a printed circuit board (PCB), a package on package (PoP) device, a first encapsulation layer, and a second encapsulation layer. The package on package (PoP) device is coupled to the printed circuit board (PCB). The package on package (PoP) device includes a first package having a first electronic package component, a second package coupled to the first package, a gap controller configured to provide a spacing between the first electronic package component and the second package. The gap controller includes a spacer and an adhesive layer. The first encapsulation layer is formed between the first package and the second package. The first encapsulation layer is configured to at least partially encapsulate the gap controller including the spacer and the adhesive layer. The second encapsulation layer is configured to at least partially encapsulates the package on package (PoP) device. The device is configured to provide cellular functionality.

公开(公告)号：US20160322332A1

公开(公告)日：2016-11-03

申请号：US14699863

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Rajneesh Kumar ,  Vladimir Noveski ,  Jie Fu ,  Ahmer Raza Syed ,  Milind Pravin Shah ,  Omar James Bchir

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some features pertain to a package that includes a redistribution portion, a first die coupled to the redistribution portion, a core layer coupled to the redistribution portion, and an encapsulation layer encapsulating the first die and the core layer. The redistribution portion includes a first dielectric layer. The core layer has a higher Young's Modulus than the encapsulation layer. In some implementations, the core layer includes a glass fiber (e.g., core layer is a glass reinforced dielectric layer). In some implementations, the core layer has a Young's Modulus of about at least 15 gigapascals (Gpa). In some implementations, the first die includes a front side and a back side, where the front side of the first die is coupled to the redistribution portion. In some implementations, the first dielectric layer is a photo imageable dielectric (PID) layer.

Abstract translation: 一些特征涉及包括再分配部分，耦合到再分配部分的第一裸片，耦合到再分配部分的核心层以及封装第一裸片和核心层的封装层的封装。 再分配部分包括第一电介质层。 核心层具有比封装层更高的杨氏模量。 在一些实施方案中，芯层包括玻璃纤维（例如，芯层是玻璃增强介电层）。 在一些实施方案中，核心层具有约至少15吉帕斯卡（Gpa）的杨氏模量。 在一些实施方案中，第一管芯包括前侧和后侧，其中第一管芯的前侧连接到再分配部分。 在一些实施方案中，第一电介质层是可光致成像电介质（PID）层。

公开(公告)号：US09460980B2

公开(公告)日：2016-10-04

申请号：US14625452

申请日：2015-02-18

Applicant: QUALCOMM Incorporated

Inventor： Sun Yun ,  Rajneesh Kumar ,  Houssam Wafic Jomaa ,  Joan Rey V. Buot

IPC: H01L21/60 ,  H01L23/367 ,  H01L23/373 ,  H01L23/528 ,  H01L25/07

CPC classification number: H01L23/3675 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L25/072 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: Some examples of the disclosure include a semiconductor package having a heat spreader, an outer perimeter portion attached to the bottom of the heat spreader along the perimeter and having a plurality of electrical pathways, a package substrate located below and spaced from the outer perimeter portion and having a plurality of electrical pathways, a plurality of connection points located between the outer perimeter component and the package substrate to provide connection points coupling the plurality of electrical pathways of the outer perimeter portion to the plurality of electrical pathways in the package substrate, and a cavity formed on the bottom of the heat spreader inside the outer perimeter portion.

Abstract translation: 本公开的一些示例包括具有散热器的半导体封装，沿着周边附接到散热器底部并具有多个电路径的外周边部分，位于外周部分下方并与外周部分隔开的封装基板， 具有多个电路径，多个连接点，位于所述外周边部件和所述封装衬底之间，以提供连接点，所述连接点将所述外周边部分的所述多个电通路连接到所述封装衬底中的所述多个电路径，以及 在外周部分内的散热器底部形成的空腔。

公开(公告)号：US20140048931A1

公开(公告)日：2014-02-20

申请号：US13787444

申请日：2013-03-06

Applicant: QUALCOMM INCORPORATED

Inventor： Rajneesh Kumar ,  Omar J. Bchir

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/4867 ,  H01L23/147 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81409 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/12042 ,  H05K3/3436 ,  H05K3/3468 ,  H05K3/3484 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

Abstract: A solder on trace device includes a conductive trace on a semiconductor substrate surface. The conductive trace has a sidewall and a bonding surface. The solder on trace device also includes a passivation layer on at least one end of the conductive trace. The solder on trace device further includes a pre-solder material on the sidewall and the bonding surface of the conductive trace.

Abstract translation: 迹线装置上的焊料包括在半导体衬底表面上的导电迹线。 导电迹线具有侧壁和接合表面。 跟踪装置上的焊料还包括在导电迹线的至少一端上的钝化层。 跟踪装置上的焊料还包括在侧壁上的预焊料材料和导电迹线的接合表面。

公开(公告)号：US11696390B2

公开(公告)日：2023-07-04

申请号：US17100121

申请日：2020-11-20

Applicant: QUALCOMM Incorporated

Inventor： Jeahyeong Han ,  Suhyung Hwang ,  Mina Iskander ,  Rajneesh Kumar ,  Darryl Sheldon Jessie

IPC: H01Q1/22 ,  H01Q1/52 ,  H01Q21/29 ,  H01Q23/00 ,  H05K1/02 ,  H01Q1/48 ,  H01Q21/06 ,  H05K1/18

CPC classification number: H05K1/0219 ,  H01Q1/2283 ,  H01Q1/48 ,  H01Q1/526 ,  H01Q21/061 ,  H05K1/0225 ,  H05K1/0227 ,  H05K1/0278 ,  H01Q21/29 ,  H01Q23/00 ,  H05K1/181 ,  H05K2201/09609 ,  H05K2201/09681 ,  H05K2201/10098

Abstract: Systems for shielding bent signal lines provide ways to couple different antenna arrays for radio frequency (RF) integrated circuits (ICs) (RFICs) associated therewith where the antenna arrays are oriented in different directions. Because the antenna arrays are oriented in different directions, the antenna structures containing the antennas may be arranged in different planes, and signal lines extending therebetween may include a bend. To prevent electromagnetic interference (EMI) or electromagnetic crosstalk (EMC) from negatively impacting signals on the signal lines, the signal lines may be shielded. The shields may further include vias connecting the mesh ground planes and positioned exteriorly of the signal lines. The density of the vias may be varied to provide a desired rigidity in planes containing the antenna arrays while providing a desired flexibility at a desired bending location in the signal lines to help bending process accuracy.

公开(公告)号：US11495873B2

公开(公告)日：2022-11-08

申请号：US16810621

申请日：2020-03-05

Applicant: QUALCOMM Incorporated

Inventor： Jeahyeong Han ,  Rajneesh Kumar ,  Suhyung Hwang ,  Jaehyun Yeon ,  Mohammad Ali Tassoudji ,  Darryl Sheldon Jessie ,  Ameya Galinde

IPC: H01Q1/22 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L23/66 ,  H01Q1/36 ,  H01Q1/52 ,  H05K1/18 ,  H05K9/00 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16

Abstract: A device that includes a first substrate comprising a first antenna, an integrated device coupled to the first substrate, an encapsulation layer located over the first substrate and the integrated device, a second substrate comprising a second antenna, and a flexible connection coupled to the first substrate and the second substrate. The device includes a shield formed over a surface of the encapsulation layer and a surface of the first substrate. The shield includes an electromagnetic interference (EMI) shield.

公开(公告)号：US11139224B2

公开(公告)日：2021-10-05

申请号：US16704789

申请日：2019-12-05

Applicant: QUALCOMM Incorporated

Inventor： Chaoqi Zhang ,  Rajneesh Kumar ,  Li-Sheng Weng ,  Darryl Sheldon Jessie ,  Suhyung Hwang ,  Jeahyeong Han ,  Xiaoming Chen ,  Jaehyun Yeon

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/56 ,  H01L21/67 ,  H01L23/31

Abstract: A package that includes a substrate having a routing region and a non-routing region along a periphery of the substrate. The non-routing region includes a plurality of vias configured as a shield. The package includes an integrated device coupled to the substrate, and an encapsulation layer located over the substrate such that the encapsulation layer encapsulates the integrated device.

公开(公告)号：US10037941B2

公开(公告)日：2018-07-31

申请号：US14610876

申请日：2015-01-30

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Noveski ,  Milind Pravin Shah ,  Rajneesh Kumar

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/5283 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/03602 ,  H01L2224/03914 ,  H01L2224/05546 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/1111 ,  H01L2224/11334 ,  H01L2224/11438 ,  H01L2224/13007 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16111 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/2711 ,  H01L2224/27438 ,  H01L2224/29006 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81101 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2924/2064 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An integrated device package that includes a die, a substrate, a fill and a conductive interconnect. The die includes a pillar, where the pillar has a first pillar width. The substrate (e.g., package substrate, interposer) includes a dielectric layer and a substrate interconnect (e.g., surface interconnect, embedded interconnect). The fill is located between the die and the substrate. The conductive interconnect is located within the fill. The conductive interconnect includes a first interconnect width that is about the same or less than the first pillar width. The conductive interconnect is coupled to the pillar and the substrate interconnect. The fill is a non-conductive photosensitive material. The fill is a photosensitive film. The substrate interconnect includes a second interconnect width that is equal or greater than the first pillar width. The conductive interconnect includes one of at least a paste, a solder and/or an enhanced solder comprising a polymeric material.

公开(公告)号：US09355898B2

公开(公告)日：2016-05-31

申请号：US14447399

申请日：2014-07-30

Applicant: QUALCOMM Incorporated

Inventor： Rajneesh Kumar ,  Houssam Wafic Jomaa ,  David Fraser Rae ,  Layal Rouhana ,  Omar James Bchir

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/495 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L21/76852 ,  H01L21/4825 ,  H01L21/76879 ,  H01L23/4952 ,  H01L23/49527 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/53204 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/00014

Abstract: Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad.

Abstract translation: 一些特征涉及集成器件，其包括第一衬底，耦合到第一衬底的第一阻焊层，耦合到第一阻焊层的第二阻焊层和第一和第二阻焊层中的开口， 开口，其包括完全被第二阻焊层覆盖的侧壁，其中第二阻焊层的侧壁覆盖第一阻焊层的侧壁。 在一些实施方案中，开口至少部分地填充有导电材料。 导电材料包括焊料和/或互连中的一种。 集成器件包括耦合到导电材料的第一互连。 第一互连是至少焊料和/或互连球之一。 在一些实施方案中，集成器件包括耦合到衬底的焊盘和耦合到焊盘的第一互连。

公开(公告)号：US20140138826A1

公开(公告)日：2014-05-22

申请号：US13790728

申请日：2013-03-08

Applicant: QUALCOMM INCORPORATED

Inventor： Rajneesh Kumar

IPC: H01L23/498 ,  H01L25/00

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A bare-die first package includes a patterned insulating layer that exposes first package balls in vias. The vias enable a second package to be positioned on the first package in a proper ball-to-ball alignment without the need for flattening or coining.

Abstract translation: 裸裸裸片第一封装包括图案化绝缘层，其在通孔中暴露第一封装球。 通孔能够使第二包装以适当的球对球定位而定位在第一包装上，而不需要平整或压印。