- Patent Title: Mechanism for device interoperability of switches in computer buses
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Application No.: US16673259Application Date: 2019-11-04
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Publication No.: US11216404B2Publication Date: 2022-01-04
- Inventor: Mahesh Natu
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: G06F13/42
- IPC: G06F13/42 ; H04L12/40

Abstract:
Apparatuses, methods, and computer-readable media are provided for operating a port manager to detect a first link condition or a second link condition of a circuitry. Under the first link condition, a first link between a downstream port of the circuitry and an upstream port of a switch is compatible to a first protocol, and a second link between a downstream port of the switch and an upstream port of a device is compatible to the second protocol. Under the second link condition, the first link exists and is compatible to the first protocol, while there is no second link being compatible to the second protocol. The port manager is to operate the downstream port of the circuitry according to the second protocol on detection of the first link condition, or according to the first protocol on detection of the second link condition. Other embodiments may be described and/or claimed.
Public/Granted literature
- US20200065290A1 MECHANISM FOR DEVICE INTEROPERABILITY OF SWITCHES IN COMPUTER BUSES Public/Granted day:2020-02-27
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