Invention Grant
- Patent Title: Multi-chip package with reduced calibration time and ZQ calibration method thereof
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Application No.: US17012845Application Date: 2020-09-04
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Publication No.: US11217283B2Publication Date: 2022-01-04
- Inventor: Junha Lee , Seonkyoo Lee , Jeongdon Ihm , Byunghoon Jeong
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Harness, Dickey & Pierce, PLC
- Priority: KR10-2019-0108936 20190903
- Main IPC: G11C7/10
- IPC: G11C7/10 ; H01L25/065 ; H01L25/18 ; H01L23/00

Abstract:
A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.
Public/Granted literature
- US20210065753A1 MULTI-CHIP PACKAGE WITH REDUCED CALIBRATION TIME AND ZQ CALIBRATION METHOD THEREOF Public/Granted day:2021-03-04
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