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公开(公告)号：US12301236B2
公开(公告)日：2025-05-13
申请号：US18331223
申请日：2023-06-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Daehoon Na , Seonkyoo Lee , Seungjun Bae , Taesung Lee
Abstract: An equalizer includes a first pulse width controller that is configured to generate a first signal by increasing a first pulse width of a first data signal having a first logic level, the first data signal corresponding to a current data bit, a second pulse width controller that is configured to generate a second signal by increasing a second pulse width of the first data signal having a second logic level, a first sampler that is configured to generate a first sampled signal by sampling the first signal, a second sampler that is configured to generate a second sampled signal by sampling the second signal, and a multiplexer that is configured to output the first sampled signal or the second sampled signal based on a value of a previous data bit.
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公开(公告)号：US11127462B2
公开(公告)日：2021-09-21
申请号：US16834025
申请日：2020-03-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junha Lee , Seonkyoo Lee , Jeongdon Ihm , Byunghoon Jeong
IPC: G11C16/06 , H01L23/66 , H01L25/065 , H01L25/18 , H01L23/00
Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.
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公开(公告)号：US11550498B2
公开(公告)日：2023-01-10
申请号：US17030635
申请日：2020-09-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tongsung Kim , Jangwoo Lee , Seonkyoo Lee , Chiweon Yoon , Jeongdon Ihm
Abstract: A storage device includes NVM package and a controller connected to the NVM package through a channel and controlling operation of the NVM package. The NVM package includes an interface chip, first NVM devices connected to the interface chip through a first internal channel and second NVM devices connected to the interface chip through a second internal channel. The interface chip selects the first internal channel in response to an operation request received from the controller and connects the first internal channel to the channel. The interface chip also determines whether retraining is necessary in relation to the second internal channel and transmits a retraining request to the controller when retraining is necessary.
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公开(公告)号：US11372593B2
公开(公告)日：2022-06-28
申请号：US17168620
申请日：2021-02-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seonkyoo Lee , Jeongdon Ihm , Chiweon Yoon , Byunghoon Jeong
Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.
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公开(公告)号：US20210320664A1
公开(公告)日：2021-10-14
申请号：US17077891
申请日：2020-10-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Anil Kavala , Seonkyoo Lee , Taesung Lee , Jeongdon Ihm , Byunghoon Jeong
Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.
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Patent Agency Ranking
公开(公告)号：US20250119149A1
公开(公告)日：2025-04-10
申请号：US18897676
申请日：2024-09-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tongsung Kim , Hyeseong Shin , Hyunwoo Ahn , Seonkyoo Lee , Hyunsung Lee , Daechul Jeong
Abstract: A memory chip performs phase calibration and duty cycle correction operations using first and second loop circuits. The first loop circuit includes a phase detector, a first counter, and a delay cell. The second loop circuit includes a phase generator, the phase detector, a second counter, and a duty correction circuit (DCC).
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公开(公告)号：US20250078888A1
公开(公告)日：2025-03-06
申请号：US18791722
申请日：2024-08-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tongsung Kim , Woojung Kim , Seonkyoo Lee
Abstract: A memory device correcting a data strobe signal when performing a write operation includes a correction circuit configured to receive the data strobe signal and to generate a reference delay for the received data strobe signal, and a main circuit configured to correct the data strobe signal based on the reference delay generated by the correction circuit. The correction circuit includes a delay cell configured to generate a reference delay for the data strobe signal received by the main circuit and to store the generated reference delay, when a data signal is input to the main circuit, a first counter configured to adjust the reference delay, and a second counter configured to determine a delay of the data strobe signal received by the main circuit, when a write operation is performed.
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公开(公告)号：US12210773B2
公开(公告)日：2025-01-28
申请号：US17528285
申请日：2021-11-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngmin Jo , Tongsung Kim , Chiweon Yoon , Seonkyoo Lee , Byunghoon Jeong
Abstract: A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.
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公开(公告)号：US11810638B2
公开(公告)日：2023-11-07
申请号：US17410210
申请日：2021-08-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seonkyoo Lee , Chiweon Yoon , Byunghoon Jeong , Youngmin Jo
IPC: G11C7/10 , H01L25/065 , G06F13/42
CPC classification number: G11C7/1048 , H01L25/0657 , G06F13/4282 , G11C2207/12 , H01L2225/06506 , H01L2225/06562
Abstract: An operating method of a memory device includes selecting a receiver from a plurality of receivers of each memory chip of a plurality of memory chips included in the memory device as a first receiver. The plurality of memory chips share a plurality of data signal lines, each memory chip includes a plurality of on-die termination (ODT) resistors, and the plurality of ODT resistors are respectively connected to the plurality of receivers of each memory chip. The method further includes setting each ODT resistor which is connected to a first receiver to a first resistance value, setting ODT resistors which are connected to receivers which are not first receivers to a second resistance value, and setting an amplification strength of an equalizer circuit of each first receiver by performing training operations. Each data signal line of the plurality of data signal lines is respectively connected to a first receiver.
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公开(公告)号：US11756592B2
公开(公告)日：2023-09-12
申请号：US17477931
申请日：2021-09-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngmin Jo , Byunghoon Jeong , Tongsung Kim , Chiweon Yoon , Seonkyoo Lee
IPC: G11C7/10
CPC classification number: G11C7/1048 , G11C7/109 , G11C7/1039 , G11C7/1057 , G11C7/1063 , G11C7/1084
Abstract: A memory device includes a memory cell array, a page buffer, a control logic circuit, a plurality of input/output pins, a data bus inversion (DBI) pin, and an interface circuit. The page buffer is connected to the memory cell array. The control logic circuit is configured to control an operation of the memory cell array. The plurality of input/output pins receive a plurality of data signals from the controller. The DBI pin receives a DBI signal from the controller. The interface circuit count a first number of bits having a logic value of 1 and a second number of bits having a logic value of 0 from the data signals and the DBI signal and provide the data signals to the page buffer or the control logic circuit based on the first number and the second number.
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