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    SEMICONDUCTOR DEVICE INCLUDING DELAY COMPENSATION CIRCUIT
    3.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING DELAY COMPENSATION CIRCUIT 有权

    公开(公告)号：US20230091026A1

    公开(公告)日：2023-03-23

    申请号：US17994296

    申请日：2022-11-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Seonkyoo Lee ,  Taesung Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

    IPC: H03L7/081 ,  H03L7/085 ,  H03K5/133 ,  G11C7/22

    Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

    Memory system performing training operation
    5.
    发明授权
    Memory system performing training operation 有权

    公开(公告)号：US10262708B2

    公开(公告)日：2019-04-16

    申请号：US15825504

    申请日：2017-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byunghoon Jeong ,  Jeongdon Ihm

    IPC: G11C8/12 ,  H01L21/822 ,  G11C16/16 ,  H01L27/11556 ,  G11C16/04 ,  G11C7/22 ,  G11C29/02 ,  G11C16/34 ,  H01L27/06 ,  H01L21/3213

    Abstract: A memory system may include a nonvolatile memory device and a controller. The nonvolatile memory device may include a data area and a device information area, the device information area being inaccessible accessed by a host. The controller may be configured to perform the training operation with respect to a data signal transmitted to or received from the nonvolatile memory device based on training information stored in the device information area. The controller may be configured to select one of a first training operation and a second training operation based on an identification code of the training information, and to perform the selected one of the first training operation based on a rooted training code generated by the controller and the second training operation based on a dynamic training code of the training information, the second training operation including performing a fewer number of searches than the first training operation.

    HIGH VOLTAGE SWITCH AND A NONVOLATILE MEMORY DEVICE INCLUDING THE SAME
    6.
    发明申请
    HIGH VOLTAGE SWITCH AND A NONVOLATILE MEMORY DEVICE INCLUDING THE SAME 有权
    高电压开关和非易失性存储器件，包括它们

    公开(公告)号：US20140204676A1

    公开(公告)日：2014-07-24

    申请号：US14077769

    申请日：2013-11-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taehyun Kim ,  Youngsun Min ,  Bilal Ahmad Janjua ,  Jeongdon Ihm

    IPC: G11C16/30

    CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/12

    Abstract: A high voltage switch of a nonvolatile memory device includes a depletion type NMOS transistor configured to switch a second driving voltage in response to an output signal of the high voltage switch; at least one inverter configured to convert a voltage of an input signal of the high voltage switch into a first driving voltage or a ground voltage, wherein the first and second driving voltages are received from an external device; and a PMOS transistor configured to transfer the second driving voltage provided to a first terminal of the PMOS transistor from the depletion type NMOS transistor to a second terminal of the PMOS transistor as the output signal in response to an output of the at least one inverter, wherein the output of the at least one inverter is transferred to a gate terminal of the PMOS transistor.

    Abstract translation: 非易失性存储器件的高电压开关包括耗尽型NMOS晶体管，其配置为响应于高电压开关的输出信号而切换第二驱动电压; 至少一个反相器，被配置为将高压开关的输入信号的电压转换为第一驱动电压或接地电压，其中从外部装置接收第一和第二驱动电压; 以及PMOS晶体管，被配置为响应于所述至少一个反相器的输出，将提供给所述PMOS晶体管的第一端子的所述第二驱动电压从所述耗尽型NMOS晶体管传送到所述PMOS晶体管的第二端子作为所述输出信号， 其中所述至少一个反相器的输出被传送到所述PMOS晶体管的栅极端子。

    MEMORY DEVICE AND MEMORY SYSTEM
    7.
    发明申请
    MEMORY DEVICE AND MEMORY SYSTEM 有权

    公开(公告)号：US20250060886A1

    公开(公告)日：2025-02-20

    申请号：US18805709

    申请日：2024-08-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-Heung Kim ,  ChangSik Yoo ,  Jeongdon Ihm ,  Hyongryol Hwang

    IPC: G06F3/06

    Abstract: A memory device includes at least one bank including at least a first sub-bank and a second sub-bank disposed in a wordline direction. The first sub-bank may include a normal data region connected to a plurality of first wordlines and storing normal data, the second sub-bank may include a metadata region connected to a plurality of second wordlines and storing metadata corresponding to the normal data, the plurality of first wordlines may match the plurality of second wordlines to form a plurality of wordline pairs, and the first sub-bank and the second sub-bank may share a row hammer region storing a number of access times to the plurality of wordline pairs.

    Storage device and retraining method thereof
    9.
    发明授权
    Storage device and retraining method thereof 有权

    公开(公告)号：US11550498B2

    公开(公告)日：2023-01-10

    申请号：US17030635

    申请日：2020-09-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Tongsung Kim ,  Jangwoo Lee ,  Seonkyoo Lee ,  Chiweon Yoon ,  Jeongdon Ihm

    IPC: G06F3/06 ,  G06K9/62

    Abstract: A storage device includes NVM package and a controller connected to the NVM package through a channel and controlling operation of the NVM package. The NVM package includes an interface chip, first NVM devices connected to the interface chip through a first internal channel and second NVM devices connected to the interface chip through a second internal channel. The interface chip selects the first internal channel in response to an operation request received from the controller and connects the first internal channel to the channel. The interface chip also determines whether retraining is necessary in relation to the second internal channel and transmits a retraining request to the controller when retraining is necessary.

    Nonvolatile memory device supporting high-efficiency I/O interface
    10.
    发明授权
    Nonvolatile memory device supporting high-efficiency I/O interface 有权

    公开(公告)号：US11372593B2

    公开(公告)日：2022-06-28

    申请号：US17168620

    申请日：2021-02-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seonkyoo Lee ,  Jeongdon Ihm ,  Chiweon Yoon ,  Byunghoon Jeong

    IPC: G06F3/06 ,  G11C16/26 ,  G06F1/06 ,  G11C16/04 ,  G11C16/10 ,  G06F13/16

    Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

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