- Patent Title: Memory arrays with vertical transistors and the formation thereof
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Application No.: US16522390Application Date: 2019-07-25
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Publication No.: US11222975B2Publication Date: 2022-01-11
- Inventor: Fatma Arzum Simsek-Ege , Steve V. Cole , Scott J. Derner , Toby D. Robbs
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L27/108 ; H01L27/11587 ; G11C11/22 ; G11C11/4091

Abstract:
An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.
Public/Granted literature
- US20210028308A1 MEMORY ARRAYS WITH VERTICAL TRANSISTORS AND THE FORMATION THEREOF Public/Granted day:2021-01-28
Information query
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