公开(公告)号：US20220131003A1

公开(公告)日：2022-04-28

申请号：US17568133

申请日：2022-01-04

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Steve V. Cole ,  Scott J. Derner ,  Toby D. Robbs

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/108 ,  H01L27/11587 ,  G11C11/22 ,  G11C11/4091

Abstract: An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.

公开(公告)号：US20220130449A1

公开(公告)日：2022-04-28

申请号：US17573271

申请日：2022-01-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toby D. Robbs ,  Charles L. Ingalls

IPC: G11C11/4091 ,  H01L27/108 ,  G11C11/4097

Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.

公开(公告)号：US20250118352A1

公开(公告)日：2025-04-10

申请号：US18746447

申请日：2024-06-18

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Toby D. Robbs ,  Christopher J. Kawamura ,  Kang-Yong Kim

IPC: G11C11/4091 ,  G11C5/06 ,  G11C11/4097

Abstract: Single (1 T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

公开(公告)号：US11581035B2

公开(公告)日：2023-02-14

申请号：US17184345

申请日：2021-02-24

Applicant: Micron Technology, Inc.

Inventor： Jiyun Li ,  Toby D. Robbs

IPC: G11C7/10 ,  G11C11/4097 ,  G11C11/4096 ,  G11C11/408

Abstract: A memory device may include a memory array having a plurality of memory cells and a first column plane having multiple column select lines. The first column select lines of the first column plane may access a first set of the memory cells associated with the first column plane. Additionally, the memory device may include a second column plane having a multiple column select lines to access a second set of the memory cells associated with the second column plane. The memory device may also include a column select line shared between the first column plane and the second column plane. The column select line may access a third set of the memory cells associated with the first column plane and a fourth set of the memory cells associated with the second column plane.

公开(公告)号：US20210028308A1

公开(公告)日：2021-01-28

申请号：US16522390

申请日：2019-07-25

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Steve V. Cole ,  Scott J. Derner ,  Toby D. Robbs

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/108 ,  H01L27/11587 ,  G11C11/22 ,  G11C11/4091

Abstract: An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.

公开(公告)号：US20250118358A1

公开(公告)日：2025-04-10

申请号：US18746339

申请日：2024-06-18

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Toby D. Robbs ,  Christopher J. Kawamura ,  Kang-Yong Kim

IPC: G11C11/4097 ,  G11C7/06 ,  G11C7/18

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

公开(公告)号：US20240413841A1

公开(公告)日：2024-12-12

申请号：US18738499

申请日：2024-06-10

Applicant: Micron Technology, Inc.

Inventor： Jiyun Li ,  Toby D. Robbs

IPC: H03M13/11 ,  H03M13/00

Abstract: Apparatuses and methods for on-device error correction implemented in a memory. A memory may have a first column plane comprising a first number of bit lines and a parity column plane that has a second number of parity bit lines in which the first number is different than the second number. In an access operation, a column select signal may activate the first number of bit lines in the first column plane and the second number of parity bit lines in the second column plane.

公开(公告)号：US11715513B2

公开(公告)日：2023-08-01

申请号：US17573271

申请日：2022-01-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toby D. Robbs ,  Charles L. Ingalls

IPC: H10B12/00 ,  G11C11/4091 ,  G11C11/4097

CPC classification number: G11C11/4091 ,  G11C11/4097 ,  H10B12/50

Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.

公开(公告)号：US20200211625A1

公开(公告)日：2020-07-02

申请号：US16814863

申请日：2020-03-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toby D. Robbs ,  Charles L. Ingalls

IPC: G11C11/4091 ,  H01L27/108 ,  G11C11/4097

Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.

公开(公告)号：US20220270668A1

公开(公告)日：2022-08-25

申请号：US17184345

申请日：2021-02-24

Applicant: Micron Technology, Inc.

Inventor： Jiyun Li ,  Toby D. Robbs

IPC: G11C11/4097 ,  G11C11/408 ,  G11C11/4096

Abstract: A memory device may include a memory array having a plurality of memory cells and a first column plane having multiple column select lines. The first column select lines of the first column plane may access a first set of the memory cells associated with the first column plane. Additionally, the memory device may include a second column plane having a multiple column select lines to access a second set of the memory cells associated with the second column plane. The memory device may also include a column select line shared between the first column plane and the second column plane. The column select line may access a third set of the memory cells associated with the first column plane and a fourth set of the memory cells associated with the second column plane.