Invention Grant
- Patent Title: Reference voltage buffer with settling enhancement
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Application No.: US17065526Application Date: 2020-10-08
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Publication No.: US11233513B2Publication Date: 2022-01-25
- Inventor: Hung-Chieh Tsai , Sheng-Hui Liao
- Applicant: MEDIATEK INC.
- Applicant Address: TW Hsin-Chu
- Assignee: MEDIATEK INC.
- Current Assignee: MEDIATEK INC.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Main IPC: G05F1/10
- IPC: G05F1/10 ; G05F3/02 ; H03K19/0185 ; G05F3/24

Abstract:
The present invention provides a reference voltage buffer comprises a reference voltage generator, a first operational amplifier, a first transistor, a first group of resistors, a first load, a second transistor, a second group of resistors and a second load. In the reference voltage buffer, the first load and the second load use active device to increase the settling time, and the first load, the second load and the reference voltage generator of the reference voltage buffer are resigned to have the same characteristics in response to the temperature variation to overcome the PVT issue, and the first load and the second load of the reference voltage buffer use the open-loop design to have large full-scale of the output reference voltages.
Public/Granted literature
- US20210135673A1 REFERENCE VOLTAGE BUFFER WITH SETTLING ENHANCEMENT Public/Granted day:2021-05-06
Information query
IPC分类: