- 专利标题： Phase skipping technique for high-speed, high-phase number delay locked loop
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申请号： US17315506申请日： 2021-05-10
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公开(公告)号： US11233519B1公开(公告)日： 2022-01-25
- 发明人: Jerry Yee-Tung Lam , Sadok Aouini , Marinette Besson , Matthew Baby Varghese
- 申请人： Ciena Corporation
- 申请人地址： US MD Hanover
- 专利权人： Ciena Corporation
- 当前专利权人： Ciena Corporation
- 当前专利权人地址： US MD Hanover
- 代理机构： Clements Bernard Baratta
- 代理商 Lawrence A. Baratta, Jr.; Christopher L. Bernard
- 主分类号： H03L7/081
- IPC分类号： H03L7/081 ; G06F1/06 ; H03L7/093
摘要：
A delay locked loop (DLL) circuit includes inputs from M-phase clocks, M is an integer that is greater than or equal to 1; N delay cells in each of M separate delay lines, one delay line for each of the inputs from the M-phase clocks, and each of the N delay cells having a delay of k*Δt, N is an integer, and k is an integer that is coprime with both N and M; N outputs for clock phases from the N delay cells; and an alignment circuit connected to outputs of the M separate delay lines and the inputs from the M-phase clocks and configured to provide phase locking.
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