Invention Grant
- Patent Title: Chip package structure
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Application No.: US16849999Application Date: 2020-04-16
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Publication No.: US11239168B2Publication Date: 2022-02-01
- Inventor: Hsin-Han Lin , Yu-Min Lin , Tao-Chih Chang
- Applicant: Industrial Technology Research Institute
- Applicant Address: TW Hsinchu
- Assignee: Industrial Technology Research Institute
- Current Assignee: Industrial Technology Research Institute
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Priority: TW108147206 20191223
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/367 ; H01L23/31 ; H01L25/065

Abstract:
A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer.
Public/Granted literature
- US20210035914A1 CHIP PACKAGE STRUCTURE Public/Granted day:2021-02-04
Information query
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