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    CHIP PACKAGE STRUCTURE
    1.
    发明申请
    CHIP PACKAGE STRUCTURE 有权

    公开(公告)号：US20210035914A1

    公开(公告)日：2021-02-04

    申请号：US16849999

    申请日：2020-04-16

    申请人： Industrial Technology Research Institute

    发明人： Hsin-Han Lin ,  Yu-Min Lin ,  Tao-Chih Chang

    IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L23/367

    摘要： A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer.

    POWER MODULE AND MANUFACTURING METHOD THEREOF
    4.
    发明公开
    POWER MODULE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230352361A1

    公开(公告)日：2023-11-02

    申请号：US17732428

    申请日：2022-04-28

    申请人： Industrial Technology Research Institute

    发明人： Hsin-Han Lin ,  Tai-Jyun Yu

    IPC分类号： H01L23/373 ,  H01L21/48 ,  H01L23/538

    CPC分类号： H01L23/3735 ,  H01L21/4857 ,  H01L23/5383 ,  H01L24/29

    摘要： Provided are a power module and a manufacturing method thereof. The power module includes an insulating substrate, a first, a second and a third conductive layers, a first thermal interface material layer, a first and a second chips and a thermal conductive layer. The insulating substrate has a first and a second surfaces opposite to each other. The first and the second conductive layers are disposed on the first surface, and electrically separated from each other. The first thermal interface material layer is disposed on the first conductive layer. The third conductive layer is disposed on the first thermal interface material layer. The first chip is disposed on the third conductive layer and electrically connected to the third conductive layer. The second chip is disposed on the second conductive layer and electrically connected to the second conductive layer. The thermal conductive layer is disposed on the second surface.

    Chip package structure
    5.
    发明授权
    Chip package structure 有权

    公开(公告)号：US11239168B2

    公开(公告)日：2022-02-01

    申请号：US16849999

    申请日：2020-04-16

    申请人： Industrial Technology Research Institute

    发明人： Hsin-Han Lin ,  Yu-Min Lin ,  Tao-Chih Chang

    IPC分类号： H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L25/065

    摘要： A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer.