Invention Grant
- Patent Title: Methods of fabricating semiconductor devices for tightening spacing between nanosheets in GAA structures and structures formed thereby
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Application No.: US16454598Application Date: 2019-06-27
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Publication No.: US11244871B2Publication Date: 2022-02-08
- Inventor: Kuo-Cheng Chiang , Chung-Wei Hsu , Lung-Kun Chu , Mao-Lin Huang , Jia-Ni Yu , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L21/02 ; H01L27/092 ; H01L29/423 ; H01L29/66 ; H01L29/78

Abstract:
A method of fabricating semiconductor devices includes forming a plurality of first and second semiconductor nanosheets in p-type and n-type device regions, respectively. An n-type work function layer is deposited to surround each of the first and second semiconductor nanosheets. A passivation layer is deposited on the n-type work function layer to surround each of the first and second semiconductor nanosheets. A patterned mask is formed on the passivation layer in the n-type device region, and the n-type work function layer and the passivation layer in the p-type device region are removed in an etching process using the patterned mask as an etching mask. Then, the patterned mask is removed, and a p-type work function layer is deposited to surround the first semiconductor nanosheets and to cover the passivation layer.
Information query
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