Invention Grant
- Patent Title: FPGA coprocessor with sparsity and density modules for execution of low and high parallelism portions of graph traversals
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Application No.: US16722082Application Date: 2019-12-20
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Publication No.: US11263168B2Publication Date: 2022-03-01
- Inventor: Xiaofei Liao , Hai Jin , Long Zheng , Chengbo Yang
- Applicant: Huazhong University of Science and Technology
- Applicant Address: CN Hubei
- Assignee: Huazhong University of Science and Technology
- Current Assignee: Huazhong University of Science and Technology
- Current Assignee Address: CN Hubei
- Agency: Rimon Law
- Agent Michael X. Ye
- Priority: CN201910084423.9 20190129
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F15/82 ; G06F15/78 ; G06F15/76 ; G06F16/901

Abstract:
An FPGA-based graph data processing method is provided for executing graph traversals on a graph having characteristics of a small-world network by using a first processor being a CPU and a second processor that is a FPGA and is in communicative connection with the first processor, wherein the first processor sends graph data to be traversed to the second processor, and obtains result data of the graph traversals from the second processor for result output after the second processor has completed the graph traversals of the graph data by executing level traversals, and the second processor comprises a sparsity processing module and a density processing module, the sparsity processing module operates in a beginning stage and/or an ending stage of the graph traversals, and the density processing module with a higher degree of parallelism than the sparsity processing module operates in the intermediate stage of the graph traversals.
Public/Granted literature
- US20200242072A1 FPGA-BASED GRAPH DATA PROCESSING METHOD AND SYSTEM THEREOF Public/Granted day:2020-07-30
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