Invention Grant
- Patent Title: High accuracy time stamping for multi-lane ports
-
Application No.: US16410275Application Date: 2019-05-13
-
Publication No.: US11265096B2Publication Date: 2022-03-01
- Inventor: Mark Bordogna , Janardhan Satyanarayana , Yoni Landau , Diwakar Suvvari
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: H04J3/07
- IPC: H04J3/07 ; H04J3/06 ; H04L1/00 ; H04L43/106

Abstract:
In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.
Public/Granted literature
- US20190273571A1 HIGH ACCURACY TIME STAMPING FOR MULTI-LANE PORTS Public/Granted day:2019-09-05
Information query