Invention Grant
- Patent Title: Neural network classifier using array of stacked gate non-volatile memory cells
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Application No.: US16382051Application Date: 2019-04-11
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Publication No.: US11270771B2Publication Date: 2022-03-08
- Inventor: Hieu Van Tran , Steven Lemke , Vipin Tiwari , Nhan Do , Mark Reiten
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP (US)
- Main IPC: G11C11/54
- IPC: G11C11/54 ; G11C16/10 ; G11C16/04 ; G11C16/26 ; G06N3/04 ; G11C14/00 ; G06N3/063 ; H01L27/115 ; H01L27/11521

Abstract:
A neural network device with synapses having memory cells each having source and drain regions in a semiconductor substrate with a channel region extending there between, a floating gate over an entirety of the channel region, and a first gate over the floating gate. First lines each electrically connect together the first gates in one of the memory cell rows, second lines each electrically connect together the source regions in one of the memory cell rows, and third lines each electrically connect together the drain regions in one of the memory cell columns. The synapses are configured to receive a first plurality of inputs as electrical voltages on the first lines or on the second lines, and to provide a first plurality of outputs as electrical currents on the third lines.
Public/Granted literature
- US20200242453A1 Neural Network Classifier Using Array Of Stacked Gate Non-volatile Memory Cells Public/Granted day:2020-07-30
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