Invention Grant
- Patent Title: Transfer of cachelines in a processing system based on transfer costs
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Application No.: US16700671Application Date: 2019-12-02
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Publication No.: US11275688B2Publication Date: 2022-03-15
- Inventor: Sriram Srinivasan , John Kelley , Matthew Schoenwald
- Applicant: ADVANCED MICRO DEVICES, INC.
- Applicant Address: US CA Santa Clara
- Assignee: ADVANCED MICRO DEVICES, INC.
- Current Assignee: ADVANCED MICRO DEVICES, INC.
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F12/084
- IPC: G06F12/084

Abstract:
A processing system includes a plurality of compute units, with each compute unit having an associated first cache of a plurality of first caches, and a second cache shared by the plurality of compute units. The second cache operates to manage transfers of caches between the first caches of the plurality of first caches such that when multiple candidate first caches contain a valid copy of a requested cacheline, the second cache selects the candidate first cache having the shortest total path from the second cache to the candidate first cache and from the candidate first cache to the compute unit issuing a request for the requested cacheline.
Public/Granted literature
- US20210165739A1 TRANSFER OF CACHELINES IN A PROCESSING SYSTEM BASED ON TRANSFER COSTS Public/Granted day:2021-06-03
Information query
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