公开(公告)号：US11928060B2

公开(公告)日：2024-03-12

申请号：US17666950

申请日：2022-02-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sriram Srinivasan ,  John Kelley ,  Matthew Schoenwald

IPC: G06F12/084

CPC classification number: G06F12/084 ,  G06F2212/1021 ,  G06F2212/1041

Abstract: A processing system includes a plurality of compute units, with each compute unit having an associated first cache of a plurality of first caches, and a second cache shared by the plurality of compute units. The second cache operates to manage transfers of caches between the first caches of the plurality of first caches such that when multiple candidate first caches contain a valid copy of a requested cacheline, the second cache selects the candidate first cache having the shortest total path from the second cache to the candidate first cache and from the candidate first cache to the compute unit issuing a request for the requested cacheline.

公开(公告)号：US11275688B2

公开(公告)日：2022-03-15

申请号：US16700671

申请日：2019-12-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sriram Srinivasan ,  John Kelley ,  Matthew Schoenwald

IPC: G06F12/084

Abstract: A processing system includes a plurality of compute units, with each compute unit having an associated first cache of a plurality of first caches, and a second cache shared by the plurality of compute units. The second cache operates to manage transfers of caches between the first caches of the plurality of first caches such that when multiple candidate first caches contain a valid copy of a requested cacheline, the second cache selects the candidate first cache having the shortest total path from the second cache to the candidate first cache and from the candidate first cache to the compute unit issuing a request for the requested cacheline.