Invention Grant
- Patent Title: Barrier-free interconnect structure and manufacturing method thereof
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Application No.: US16572670Application Date: 2019-09-17
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Publication No.: US11276637B2Publication Date: 2022-03-15
- Inventor: Pei-Yu Wang , Cheng-Ting Chung , Wei Ju Lee
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/522 ; H01L21/768
Abstract:
Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.
Public/Granted literature
- US20210082803A1 Barrier-Free Interconnect Structure and Manufacturing Method Thereof Public/Granted day:2021-03-18
Information query
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