公开(公告)号：US11984402B2

公开(公告)日：2024-05-14

申请号：US17870531

申请日：2022-07-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Pei-Yu Wang ,  Yu-Xuan Huang

IPC分类号： H01L23/528 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L23/5286 ,  H01L21/02603 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78696

摘要： In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.

公开(公告)号：US20230352534A1

公开(公告)日：2023-11-02

申请号：US18352133

申请日：2023-07-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Pei-Yu Wang ,  Pei-Hsun Wang

IPC分类号： H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/306 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L29/1037 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/0649 ,  H01L21/02532 ,  H01L29/66636 ,  H01L21/3065 ,  H01L29/66795 ,  H01L21/0262 ,  H01L21/76224 ,  H01L29/66545 ,  H01L29/6656 ,  H01L21/30604 ,  H01L29/785 ,  H01L27/0886 ,  H01L21/31053

摘要： A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip.

公开(公告)号：US11594612B2

公开(公告)日：2023-02-28

申请号：US17508595

申请日：2021-10-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Min Cao ,  Pei-Yu Wang ,  Sai-Hooi Yeong ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L21/00 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

摘要： The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench; depositing a first metal oxide layer over the interfacial layer; removing the first metal oxide layer from the pFET structure; depositing a ferroelectric layer in each gate trench; depositing a second metal oxide layer over the ferroelectric layer; removing the second metal oxide layer from the nFET structure; and depositing a gate electrode in each gate trench.

公开(公告)号：US20220359396A1

公开(公告)日：2022-11-10

申请号：US17870531

申请日：2022-07-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Pei-Yu Wang ,  Yu-Xuan Huang

IPC分类号： H01L23/528 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L29/06

摘要： In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.

公开(公告)号：US20220278200A1

公开(公告)日：2022-09-01

申请号：US17745655

申请日：2022-05-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Pei-Yu Wang ,  Pei-Hsun Wang

IPC分类号： H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/306 ,  H01L29/78 ,  H01L27/088

摘要： A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip.

公开(公告)号：US11410930B2

公开(公告)日：2022-08-09

申请号：US17015628

申请日：2020-09-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Pei-Yu Wang ,  Yu-Xuan Huang

IPC分类号： H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L29/66

摘要： In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.

公开(公告)号：US11177344B2

公开(公告)日：2021-11-16

申请号：US16582694

申请日：2019-09-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Pei-Yu Wang ,  Wei Ju Lee

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/78 ,  H01L21/02

摘要： A semiconductor device includes a substrate, semiconductor wires disposed over the substrate, a gate structure wrapping around each of the semiconductor wires, and an epitaxial source/drain (S/D) feature in contact with the semiconductor wires. A portion of the epitaxial S/D feature is horizontally surrounded by an air gap.

公开(公告)号：US11158721B2

公开(公告)日：2021-10-26

申请号：US16895436

申请日：2020-06-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Min Cao ,  Pei-Yu Wang ,  Sai-Hooi Yeong ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L21/00 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

摘要： The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench; depositing a first metal oxide layer over the interfacial layer; removing the first metal oxide layer from the pFET structure; depositing a ferroelectric layer in each gate trench; depositing a second metal oxide layer over the ferroelectric layer; removing the second metal oxide layer from the nFET structure; and depositing a gate electrode in each gate trench.

公开(公告)号：US20210066469A1

公开(公告)日：2021-03-04

申请号：US16895436

申请日：2020-06-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Min Cao ,  Pei-Yu Wang ,  Sai-Hooi Yeong ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L29/51 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

摘要： The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench; depositing a first metal oxide layer over the interfacial layer; removing the first metal oxide layer from the pFET structure; depositing a ferroelectric layer in each gate trench; depositing a second metal oxide layer over the ferroelectric layer; removing the second metal oxide layer from the nFET structure; and depositing a gate electrode in each gate trench.

公开(公告)号：US20240332169A1

公开(公告)日：2024-10-03

申请号：US18738236

申请日：2024-06-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Pei-Yu Wang ,  Cheng-Ting Chung ,  Wei Ju Lee

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7685 ,  H01L21/76877

摘要： Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.