公开(公告)号：US20240332169A1

公开(公告)日：2024-10-03

申请号：US18738236

申请日：2024-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Cheng-Ting Chung ,  Wei Ju Lee

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7685 ,  H01L21/76877

Abstract: Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.

公开(公告)号：US20240332022A1

公开(公告)日：2024-10-03

申请号：US18672104

申请日：2024-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Zhi-Chang Lin ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L21/28 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/28123 ,  H01L21/31055 ,  H01L21/32136 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor device includes a first fin protruding upwardly from a substrate, a second fin protruding upwardly from the substrate, a first gate structure having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate structure having a portion that at least partially wraps around the upper portion of the first fin, and a dielectric feature having a first portion between the first and second portions of the first gate structure. In a lengthwise direction of the first fin, the dielectric feature has a second portion extending to a sidewall of the second gate structure.

公开(公告)号：US20240194762A1

公开(公告)日：2024-06-13

申请号：US18586735

申请日：2024-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min Cao ,  Pei-Yu Wang ,  Sai-Hooi Yeong ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L21/0206 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6684 ,  H01L29/78391

Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.

公开(公告)号：US20230369398A1

公开(公告)日：2023-11-16

申请号：US18360974

申请日：2023-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pei-Yu Wang ,  Wei Ju Lee

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/0673 ,  H01L29/66553 ,  H01L29/6656 ,  H01L21/30604 ,  H01L29/42392 ,  H01L29/0847 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/45 ,  H01L29/785 ,  H01L29/66795 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66545 ,  H01L29/665 ,  H01L21/02532

Abstract: A semiconductor device includes a substrate, nanostructures vertically suspended above the substrate, a metal gate structure wrapping each of the nanostructures, an epitaxial feature having a first sidewall in physical contact with end portions of the nanostructures, and an air gap disposed between the epitaxial feature and the metal gate structure. The air gap exposes the first sidewall of the epitaxial feature and the end portions of the nanostructures.

公开(公告)号：US11757042B2

公开(公告)日：2023-09-12

申请号：US17671156

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Yu-Xuan Huang ,  Pei-Yu Wang ,  Cheng-Ting Chung ,  Ching-Wei Tsai ,  Hou-Yu Chen

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78618 ,  H01L21/02603 ,  H01L21/28518 ,  H01L21/31116 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78696

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

公开(公告)号：US11742387B2

公开(公告)日：2023-08-29

申请号：US17745655

申请日：2022-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Pei-Hsun Wang

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/306 ,  H01L29/78 ,  H01L27/088 ,  H01L21/3105

CPC classification number: H01L29/1037 ,  H01L21/0262 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/30604 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/31053

Abstract: A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip.

公开(公告)号：US20220262911A1

公开(公告)日：2022-08-18

申请号：US17174793

申请日：2021-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Pei-Yu Wang ,  Chi On Chui

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/775 ,  H01L29/786

Abstract: In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain (LDD) region, the first LDD region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first LDD region; an interlayer dielectric (ILD) layer over the first epitaxial source/drain region; a source/drain contact extending through the ILD layer, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.

公开(公告)号：US11387233B2

公开(公告)日：2022-07-12

申请号：US16915930

申请日：2020-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Huan-Chieh Su ,  Chun-Yuan Chen ,  Pei-Yu Wang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/08 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a source region, a drain region, and a gate electrode layer disposed between the source region and the drain region. The gate electrode layer includes a first surface facing the source region, and the first surface includes an edge portion having a first height. The gate electrode layer further includes a second surface opposite the first surface and facing the drain region. The second surface includes an edge portion having a second height. The second height is different from the first height.

公开(公告)号：US11276637B2

公开(公告)日：2022-03-15

申请号：US16572670

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Cheng-Ting Chung ,  Wei Ju Lee

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.

公开(公告)号：US11251308B2

公开(公告)日：2022-02-15

申请号：US16998576

申请日：2020-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Yu-Xuan Huang ,  Pei-Yu Wang ,  Cheng-Ting Chung ,  Ching-Wei Tsai ,  Hou-Yu Chen

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L21/285

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.