Invention Grant
- Patent Title: Multi-gate device and related methods
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Application No.: US16437643Application Date: 2019-06-11
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Publication No.: US11276695B2Publication Date: 2022-03-15
- Inventor: Kuo-Cheng Ching , Ching-Wei Tsai , Kuan-Lun Cheng , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/78 ; H01L29/66

Abstract:
A method for fabricating a semiconductor device includes providing a fin in a first region of a substrate. The fin includes a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A portion of a layer of the second type of epitaxial layers in a channel region of the first fin is removed to form a first gap between a first layer of the first type of epitaxial layers and a second layer of the first type of epitaxial layers. A first portion of a first gate structure is formed within the first gap and extending from a first surface of the first layer of the first type of epitaxial layers to a second surface of the second layer of the first type of epitaxial layers. A first source/drain feature is formed abutting the first portion of the first gate structure.
Public/Granted literature
- US20200020692A1 MULTI-GATE DEVICE AND RELATED METHODS Public/Granted day:2020-01-16
Information query
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