Invention Grant
- Patent Title: FeFET of 3D structure for capacitance matching
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Application No.: US16733398Application Date: 2020-01-03
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Publication No.: US11289602B2Publication Date: 2022-03-29
- Inventor: Hung-Li Chiang , Chih-Sheng Chang , Tzu-Chiang Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L27/088 ; H01L29/66

Abstract:
An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.
Public/Granted literature
- US20210210636A1 FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING Public/Granted day:2021-07-08
Information query
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