Invention Grant
- Patent Title: TSV-less die stacking using plated pillars/through mold interconnect
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Application No.: US16639085Application Date: 2017-09-30
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Publication No.: US11296052B2Publication Date: 2022-04-05
- Inventor: Preston T. Meyers , Javier A. Falcon , Shawna M. Liff , Joe R. Saucedo , Adel A. Elsherbini , Albert S. Lopez , Johanna M. Swan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2017/054670 WO 20170930
- International Announcement: WO2019/066986 WO 20190404
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L25/00
Abstract:
A device package has substrates disposed on top of one another to form a stack, and pads formed on at least one of the top surface and the bottom surface of each of the substrates. The device package has interconnects electrically coupling at least one of the top surface and the bottom surface of each substrate to at least one of the top surface and the bottom surface of another substrate. The device package has pillars disposed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates. The device package also has adhesive layers formed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates.
Public/Granted literature
- US20200212012A1 TSV-LESS DIE STACKING USING PLATED PILLARS/THROUGH MOLD INTERCONNECT Public/Granted day:2020-07-02
Information query
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