Invention Grant
- Patent Title: Multi-gate device and related methods
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Application No.: US16947377Application Date: 2020-07-30
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Publication No.: US11296082B2Publication Date: 2022-04-05
- Inventor: Li-Yang Chuang , Jia-Chuan You , Kuo-Cheng Chiang , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L27/088 ; H01L29/06 ; H01L29/08 ; H01L29/10 ; H01L29/66 ; H01L29/78 ; H01L21/762 ; H01L21/8234

Abstract:
A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.
Public/Granted literature
- US20220037315A1 MULTI-GATE DEVICE AND RELATED METHODS Public/Granted day:2022-02-03
Information query
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