- 专利标题: Address translation cache invalidation in a microprocessor
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申请号: US17063888申请日: 2020-10-06
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公开(公告)号: US11301392B2公开(公告)日: 2022-04-12
- 发明人: Debapriya Chatterjee , Bryant Cockcroft , Larry Leitner , John A. Schumann , Karen Yokum
- 申请人: International Business Machines Corporation
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Scully, Scott, Murphy & Presser, P. C.
- 主分类号: G06F12/10
- IPC分类号: G06F12/10 ; G06F12/02 ; G06F12/109 ; G06F12/1036
摘要:
A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.
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