Invention Grant
- Patent Title: Combined SHA2 and SHA3 based XMSS hardware accelerator
-
Application No.: US16455950Application Date: 2019-06-28
-
Publication No.: US11303429B2Publication Date: 2022-04-12
- Inventor: Santosh Ghosh , Vikram Suresh , Sanu Mathew , Manoj Sastry , Andrew H. Reinders , Raghavan Kumar , Rafael Misoczki
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- Main IPC: H04L9/06
- IPC: H04L9/06 ; G06F7/503 ; G06F9/30 ; H04L9/32
Abstract:
In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.
Public/Granted literature
- US20190319782A1 COMBINED SHA2 AND SHA3 BASED XMSS HARDWARE ACCELERATOR Public/Granted day:2019-10-17
Information query
