Invention Grant
- Patent Title: Method and apparatus to use dram as a cache for slow byte-addressible memory for efficient cloud applications
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Application No.: US17255886Application Date: 2018-09-28
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Publication No.: US11307985B2Publication Date: 2022-04-19
- Inventor: Yao Zu Dong , Kun Tian , Fengguang Wu , Jingqi Liu
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Kacvinsky Daisak Bluni PLLC
- International Application: PCT/CN2018/108206 WO 20180928
- International Announcement: WO2020/061989 WO 20200402
- Main IPC: G06F12/0802
- IPC: G06F12/0802 ; G06F3/06

Abstract:
Various embodiments are generally directed to virtualized systems. A first guest memory page may be identified based at least in part on a number of accesses to a page table entry for the first guest memory page in a page table by an application executing in a virtual machine (VM) on the processor, the first guest memory page corresponding to a first byte-addressable memory. The execution of the VM and the application on the processor may be paused. The first guest memory page may be migrated to a target memory page in a second byte-addressable memory, the target memory page comprising one of a target host memory page and a target guest memory page, the second byte-addressable memory having an access speed faster than an access speed of the first byte-addressable memory.
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