Invention Grant
- Patent Title: Zero padding apparatus for encoding variable-length signaling information and zero padding method using same
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Application No.: US17016479Application Date: 2020-09-10
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Publication No.: US11309913B2Publication Date: 2022-04-19
- Inventor: Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim
- Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Applicant Address: KR Daejeon
- Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Current Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Current Assignee Address: KR Daejeon
- Agency: NSIP Law
- Priority: KR10-2015-0028063 20150227,KR10-2016-0020867 20160222
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/11 ; H03M13/27 ; H03M13/29 ; H03M13/15 ; H03M13/25

Abstract:
A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.
Information query
IPC分类: