Invention Grant
- Patent Title: Optimized partitioning of multi-layer networks in core-based neurosynaptic architectures
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Application No.: US16140489Application Date: 2018-09-24
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Publication No.: US11315020B2Publication Date: 2022-04-26
- Inventor: Tapan K. Nayak , Arnon Amir
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Foley Hoag, LLP
- Agent Erik A. Huestis; Stephen J. Kenny
- Main IPC: G06N3/08
- IPC: G06N3/08 ; G06N3/04 ; G06N3/063

Abstract:
Hardware optimization of neural networks is provided. In various embodiments, an output-induced receptive field of each of a plurality of layers of a neural network is determined. From each of the plurality of layers any portions of their respective input that falls outside their respective output-induced receptive field are trimmed. For each of the plurality of layers, a plurality of mappings of the layer to physical neurosynaptic cores are determined. A mapping is determined having a minimum total number of cores required for the neural network based on the plurality of mappings.
Public/Granted literature
- US20200097821A1 OPTIMIZED PARTITIONING OF MULTI-LAYER NETWORKS IN CORE-BASED NEUROSYNAPTIC ARCHITECTURES Public/Granted day:2020-03-26
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