公开(公告)号：US20250028534A1

公开(公告)日：2025-01-23

申请号：US17076280

申请日：2020-10-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nathaniel Joseph McClatchey ,  Andrew Stephen Cassidy ,  Arnon Amir ,  Dharmendra S. Modha ,  Jun Sawada ,  Pallab Datta ,  Rathinakumar Appuswamy

IPC: G06F9/32 ,  G06F9/30 ,  G06N3/063

Abstract: According to embodiments of the present disclosure, processor chips adapted for efficient massively-concurrent conditional computation are provided. In various embodiments, a chip comprises at least one processing core; a controller operatively coupled to the at least one processing core; and an instruction memory in communication with the controller. The controller is configured to: concurrently compute a plurality of relational operators on a plurality of inputs, resulting in a plurality of results; combine the plurality of results to determine an index; select an operation based on the index; and cause the at least one processing core to execute the selected operation.

公开(公告)号：US10725494B2

公开(公告)日：2020-07-28

申请号：US16423928

申请日：2019-05-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Arnon Amir ,  Pallab Datta ,  Dharmendra S. Modha

IPC: G06E1/00 ,  G06N3/04 ,  G06N3/063

Abstract: Reduction in the number of neurons and axons in a neurosynaptic network while maintaining its functionality is provided. A neural network description describing a neural network is read. One or more functional unit of the neural network is identified. The one or more functional unit of the neural network is optimized. An optimized neural network description is written based on the optimized functional unit.

公开(公告)号：US10698867B2

公开(公告)日：2020-06-30

申请号：US15232597

申请日：2016-08-09

Applicant: International Business Machines Corporation

Inventor： Arnon Amir ,  David A. Pease ,  Rainer Richter

IPC: G06F3/06 ,  G11B27/032 ,  G06F16/17 ,  G06F16/18

Abstract: In one embodiment, a data storage system includes a tape drive configured to: write a plurality of files to a first partition of a magnetic recording tape; and write an index to a second partition of the magnetic recording tape, the index including information about locations of data of the plurality of files in the first partition of the magnetic recording tape. In another embodiment, a magnetic recording tape includes: a plurality of files to written to a first partition of the magnetic recording tape using a tape drive; and an index written to a second partition of the magnetic recording tape using the tape drive, the index including information about locations of data of the plurality of files in the first partition of the magnetic recording tape.

公开(公告)号：US20190278320A1

公开(公告)日：2019-09-12

申请号：US16423928

申请日：2019-05-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Arnon Amir ,  Pallab Datta ,  Dharmendra S. Modha

IPC: G06E1/00 ,  G06N3/063 ,  G06N3/04

Abstract: Reduction in the number of neurons and axons in a neurosynaptic network while maintaining its functionality is provided. A neural network description describing a neural network is read. One or more functional unit of the neural network is identified. The one or more functional unit of the neural network is optimized. An optimized neural network description is written based on the optimized functional unit.

公开(公告)号：US10204301B2

公开(公告)日：2019-02-12

申请号：US14662096

申请日：2015-03-18

Applicant: International Business Machines Corporation

Inventor： Arnon Amir ,  Rathinakumar Appuswamy ,  Pallab Datta ,  Myron D. Flickner ,  Paul A. Merolla ,  Dharmendra S. Modha ,  Benjamin G. Shaw

IPC: G06N3/04 ,  G06N3/063

Abstract: One embodiment of the invention provides a system for mapping a neural network onto a neurosynaptic substrate. The system comprises a reordering unit for reordering at least one dimension of an adjacency matrix representation of the neural network. The system further comprises a mapping unit for selecting a mapping method suitable for mapping at least one portion of the matrix representation onto the substrate, and mapping the at least one portion of the matrix representation onto the substrate utilizing the mapping method selected. The system further comprises a refinement unit for receiving user input regarding at least one criterion relating to accuracy or resource utilization of the substrate. The system further comprises an evaluating unit for evaluating each mapped portion against each criterion. Each mapped portion that fails to satisfy a criterion may be remapped to allow trades offs between accuracy and resource utilization of the substrate.

公开(公告)号：US20180219996A1

公开(公告)日：2018-08-02

申请号：US15901112

申请日：2018-02-21

Applicant: International Business Machines Corporation

Inventor： Arnon Amir ,  Nimrod Megiddo

IPC: H04M3/428 ,  H04M3/22 ,  H04M7/00

CPC classification number: H04M3/4286 ,  H04M3/2272 ,  H04M7/0012

Abstract: The present invention provides a method, system, and computer program product of managing telephone interactions of a user and an agent. In an embodiment, the present invention includes determining when a user telecommunications device is no longer in an on-hold state based on electronic signals transmitted from an agent telecommunications device, in response to the determining, receiving speech of an agent from the agent telecommunications device, in response to the receiving, transmitting an alert message to the user telecommunications device, in response to the receiving, monitoring for at least one indication that the user is about to speak with the agent, in response to the monitoring not resulting in the at least one indication, transmitting at least one utterance corresponding to the user to the agent telecommunications device, and in response to the monitoring resulting in the at least one indication, conducting a smooth transition to the user.

公开(公告)号：US09704094B2

公开(公告)日：2017-07-11

申请号：US14626677

申请日：2015-02-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Arnon Amir ,  David J. Berg ,  Pallab Datta ,  Myron D. Flickner ,  Paul A. Merolla ,  Dharmendra S. Modha ,  Benjamin G. Shaw ,  Brian S. Taba

IPC: G06N5/00 ,  G06F1/00 ,  G06N3/063 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06N3/049

Abstract: One embodiment of the invention provides a method comprising defining a brainlet representing a platform-agnostic network of neurons, synapses, and axons. The method further comprises compiling the brainlet into a corelet for mapping onto neurosynaptic substrate, and mapping the corelet onto the neurosynaptic substrate. The corelet is compatible with one or more conditions related to the neurosynaptic substrate.

公开(公告)号：US20160350017A1

公开(公告)日：2016-12-01

申请号：US15232683

申请日：2016-08-09

Applicant: International Business Machines Corporation

Inventor： Arnon Amir ,  David A. Pease ,  Rainer Richter

IPC: G06F3/06 ,  G06F17/30

Abstract: In one embodiment, a computer program product for writing data to a magnetic recording tape includes a computer readable storage medium having computer readable program code embodied therewith. The computer readable program code includes: computer readable program code configured to cause a tape drive to: write a plurality of files to a first partition of a magnetic recording tape; and write an index to a second partition of the magnetic recording tape. The index includes information about locations of data of the plurality of files in the first partition of the magnetic recording tape. A longitudinal buffering band is present between the first and second partitions; and is configured to isolate writing in the first partition from overwriting neighboring tracks in the second partition. The longitudinal buffering band comprises an entirety of at least one full wrap of the magnetic recording tape.

Abstract translation: 在一个实施例中，用于向磁记录带写入数据的计算机程序产品包括具有实施的计算机可读程序代码的计算机可读存储介质。 所述计算机可读程序代码包括：被配置为使磁带驱动器执行以下操作的计算机可读程序代码：将多个文件写入磁记录带的第一分区; 并向磁记录带的第二分区写入索引。 索引包括关于磁记录带的第一分区中的多个文件的数据的位置的信息。 纵向缓冲带存在于第一和第二隔板之间; 并且被配置为隔离第一分区中的写入以覆盖第二分区中的相邻轨道。 纵向缓冲带包括磁记录带的整个至少一个全包裹物。

公开(公告)号：US20160247062A1

公开(公告)日：2016-08-25

申请号：US14626677

申请日：2015-02-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Arnon Amir ,  David J. Berg ,  Pallab Datta ,  Myron D. Flickner ,  Paul A. Merolla ,  Dharmendra S. Modha ,  Benjamin G. Shaw ,  Brian S. Taba

IPC: G06N3/06 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06N3/049

Abstract: One embodiment of the invention provides a method comprising defining a brainlet representing a platform-agnostic network of neurons, synapses, and axons. The method further comprises compiling the brainlet into a corelet for mapping onto neurosynaptic substrate, and mapping the corelet onto the neurosynaptic substrate. The corelet is compatible with one or more conditions related to the neurosynaptic substrate.

Abstract translation: 本发明的一个实施例提供了一种方法，包括定义表示神经元，突触和轴突的平台不可知网络的脑部。 该方法还包括将该脑片编成一个芯片，以映射到神经突触底物上，并将该芯片映射到神经突触底物上。 骨架与一种或多种与神经突触底物相关的病症相容。

公开(公告)号：US20160125289A1

公开(公告)日：2016-05-05

申请号：US14528885

申请日：2014-10-30

Applicant: International Business Machines Corporation

Inventor： Arnon Amir ,  Pallab Datta ,  Paul A. Merolla ,  Dharmendra S. Modha

IPC: G06N3/04

CPC classification number: G06N3/049 ,  G06N3/063 ,  G06N3/088

Abstract: Embodiments of the invention provide a method for mapping a bipartite graph onto a neuromorphic architecture comprising of a plurality of interconnected neuromorphic core circuits. The graph includes a set of source nodes and a set of target nodes. The method comprises, for each source node, creating a corresponding splitter construct configured to duplicate input. Each splitter construct comprises a first portion of a core circuit. The method further comprises, for each target node, creating a corresponding merger construct configured to combine input. Each merger construct comprises a second portion of a core circuit. Source nodes and target nodes are connected based on a permutation of an interconnect network interconnecting the core circuits.

Abstract translation: 本发明的实施例提供了一种用于将二分图映射到包括多个互连的神经形核心电路的神经形态结构上的方法。 该图包括一组源节点和一组目标节点。 该方法包括对于每个源节点，创建配置为重复输入的相应分离器结构。 每个分离器构造包括核心电路的第一部分。 该方法还包括对于每个目标节点，创建被配置为组合输入的对应的合并构造。 每个合并构造包括核心电路的第二部分。 源节点和目标节点基于互连核心电路的互连网络的置换来连接。