Invention Grant
- Patent Title: Transistors with back-side contacts to create three dimensional memory and logic
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Application No.: US16669599Application Date: 2019-10-31
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Publication No.: US11335686B2Publication Date: 2022-05-17
- Inventor: Wilfred Gomes , Mauro J. Kobrinsky , Abhishek A. Sharma , Tahir Ghani , Doug Ingerly , Rajesh Kumar
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patent Capital Group
- Main IPC: H01L27/108
- IPC: H01L27/108

Abstract:
Described herein are IC devices that include transistors with contacts to one of the source/drain (S/D) regions being on the front side of the transistors and contacts to the other one of the S/D regions being on the back side of the transistors (i.e., “back-side contacts”). Using transistors with one front-side and one back-side S/D contacts provides advantages and enables unique architectures that were not possible with conventional front-end-of-line transistors with both S/D contacts being on one side.
Public/Granted literature
- US20210134802A1 TRANSISTORS WITH BACK-SIDE CONTACTS TO CREATE THREE DIMENSIONAL MEMORY AND LOGIC Public/Granted day:2021-05-06
Information query
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