Invention Grant
- Patent Title: Block-on-block memory array architecture using bi-directional staircases
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Application No.: US17208868Application Date: 2021-03-22
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Publication No.: US11335700B2Publication Date: 2022-05-17
- Inventor: Aaron S. Yip
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Greenberg Traurig
- Main IPC: G11C8/10
- IPC: G11C8/10 ; G11C16/26 ; H01L27/11582 ; H01L27/11556 ; H01L23/528 ; G11C16/08 ; G11C11/56 ; H01L21/768 ; H01L21/3213 ; G11C16/24
Abstract:
A memory device stores data in non-volatile memory. The memory device includes a non-volatile memory array. The memory array includes tiers for accessing data stored in blocks of the memory array, including a block having a left block portion and a right block portion. A first staircase is positioned between the left block portion and the right block portion, and a bottom portion of the first staircase includes steps corresponding to first tiers of the left block portion. A second staircase is positioned between the left block portion and the right block portion, and a top portion of the second staircase includes steps corresponding to second tiers of the right block portion. The steps of the first staircase and the steps of the second staircase descend in opposite directions.
Public/Granted literature
- US20210288071A1 BLOCK-ON-BLOCK MEMORY ARRAY ARCHITECTURE USING BI-DIRECTIONAL STAIRCASES Public/Granted day:2021-09-16
Information query
