Invention Grant
- Patent Title: High voltage tolerant circuit architecture for applications subject to electrical overstress fault conditions
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Application No.: US16700989Application Date: 2019-12-02
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Publication No.: US11342323B2Publication Date: 2022-05-24
- Inventor: Javier A. Salcedo , Linfeng He
- Applicant: Analog Devices, Inc.
- Applicant Address: US MA Norwood
- Assignee: Analog Devices, Inc.
- Current Assignee: Analog Devices, Inc.
- Current Assignee Address: US MA Norwood
- Agency: Knobbe, Martens, Olson & Bear, LLP
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H02H9/04 ; H01L29/74 ; H01L29/08 ; H01L29/417 ; H01L29/40

Abstract:
A semiconductor die with high-voltage tolerant electrical overstress circuit architecture is disclosed. One embodiment of the semiconductor die includes a signal pad, a ground pad, a core circuit electrically connected to the signal pad, and a stacked thyristor protection device. The stacked thyristor includes a first thyristor and a resistive thyristor electrically connected in a stack between the signal pad and the ground pad, which enhances the holding voltage of the circuit relatively to an implementation with only the thyristor. Further, the resistive thyristor includes a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and an electrical connection between a collector of the PNP bipolar transistor and a collector of the NPN bipolar transistor. This allows the resistive thyristor to exhibit both thyristor characteristics and resistive characteristics based on a level of current flow.
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