A non-volatile memory device includes a memory cell array, a word line driver, a bit line driver, a read circuit, and control logic. The memory cell array includes a plurality of banks. Each bank includes a plurality of tiles. Each tile includes a plurality of resistive memory cells connected to a plurality of bit lines and a plurality of word lines. The word line driver selects one of the word lines in response to an input address. The bit line driver selects one of the bit lines in response to the input address. The read circuit reads a code word from the memory cell array in a read operation. The control logic is configured to control the word line driver, the bit line driver, the read circuit in the read operation. The control logic performs an address scramble on the input address, and provides the scrambled address to the read circuit to access the plurality of tiles in the read operation.