Invention Grant
- Patent Title: Method for erasing a ReRAM memory cell
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Application No.: US17140064Application Date: 2021-01-02
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Publication No.: US11355187B2Publication Date: 2022-06-07
- Inventor: Victor Nguyen , Fethi Dhaoui , John L McCollum , Fengliang Xue
- Applicant: Microchip Technology Inc.
- Applicant Address: US AZ Chandler
- Assignee: Microchip Technology Inc.
- Current Assignee: Microchip Technology Inc.
- Current Assignee Address: US AZ Chandler
- Agency: Glass and Associates
- Agent Kenneth D'Alessandro; Kenneth Glass
- Main IPC: G11C13/00
- IPC: G11C13/00 ; H01L45/00

Abstract:
A method for erasing a ReRAM memory cell that includes a ReRAM device having a select circuit with two series-connected select transistors. The method includes determining if the ReRAM cell is selected for erasing. If the ReRAM cell is selected for erasing, the bit line node is biased at a first voltage potential, the source line node is biased at a second voltage potential greater than the first voltage potential and the gates of the series-connected select transistors are supplied with positive voltage pulses. The difference between the first voltage potential and the second voltage potential is sufficient to erase the ReRAM device in the ReRAM cell. If the ReRAM cell is unselected for erasing, the gate of the one of the series-connected select transistors having its drain connected to an electrode of the ReRAM device is supplied with a voltage potential insufficient to turn it on.
Public/Granted literature
- US20210125666A1 ReRAM MEMORY CELL HAVING DUAL WORD LINE CONTROL AND METHOD FOR ERASING A ReRAM MEMORY CELL Public/Granted day:2021-04-29
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