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公开(公告)号：US20220262434A1
公开(公告)日：2022-08-18
申请号：US17736563
申请日：2022-05-04
Applicant: Microchip Technology Inc.
Inventor： Victor Nguyen , Fethi Dhaoui , John L. McCollum , Fengliang Xue
Abstract: A ReRAM memory array includes ReRAM memory cells and a select circuit having two series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for erasing, the bit line coupled to the ReRAM memory cell(s) to be erased is biased at a first voltage potential. The source line coupled to the ReRAM memory cell(s) to be erased is biased at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device. The gates of the series-connected select transistors coupled to the ReRAM memory cell(s) to be erased are supplied with positive voltage pulses. The gates of the series-connected select transistors coupled to the ReRAM memory cell(s) unselected for erasing are supplied with a voltage potential insufficient to turn them on.
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2.发明申请公开(公告)号：US20210125666A1
公开(公告)日：2021-04-29
申请号：US17140064
申请日：2021-01-02
Applicant: Microchip Technology Inc.
Inventor： Victor Nguyen , Fethi Dhaoui , John L McCollum , Fengliang Xue
Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.
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3.发明申请公开(公告)号：US20200327938A1
公开(公告)日：2020-10-15
申请号：US16405936
申请日：2019-05-07
Applicant: Microchip Technology Inc.
Inventor： Fengliang Xue , Fethi Dhaoui , Victor Nguyen , John L. McCollum
IPC: G11C13/00
Abstract: A method for programming a resistive random-access memory (ReRAM) cell includes passing a first current through the ReRAM device for a first period of time, the first current selected to create a leakage path through the ReRAM device, and after passing the first current through the ReRAM device passing a second current through the ReRAM device for a second period of time shorter than the first period of time, the second current selected to create a current path having a desired resistance through the leakage path through the ReRAM device.
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Patent Agency Ranking
公开(公告)号：US12154622B2
公开(公告)日：2024-11-26
申请号：US17736563
申请日：2022-05-04
Applicant: Microchip Technology Inc.
Inventor： Victor Nguyen , Fethi Dhaoui , John L McCollum , Fengliang Xue
Abstract: A ReRAM memory array includes ReRAM memory cells having two series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for erasing, the bit line coupled to the ReRAM memory cell(s) to be erased is biased at a first voltage potential. The source line coupled to the ReRAM memory cell(s) to be erased is biased at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device. The gates of the series-connected select transistors of the ReRAM memory cell(s) to be erased are supplied with positive voltage pulses. The gates of the series-connected select transistors of the ReRAM memory cell(s) unselected for erasing are supplied with a voltage potential insufficient to turn them on.
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公开(公告)号：US11355187B2
公开(公告)日：2022-06-07
申请号：US17140064
申请日：2021-01-02
Applicant: Microchip Technology Inc.
Inventor： Victor Nguyen , Fethi Dhaoui , John L McCollum , Fengliang Xue
Abstract: A method for erasing a ReRAM memory cell that includes a ReRAM device having a select circuit with two series-connected select transistors. The method includes determining if the ReRAM cell is selected for erasing. If the ReRAM cell is selected for erasing, the bit line node is biased at a first voltage potential, the source line node is biased at a second voltage potential greater than the first voltage potential and the gates of the series-connected select transistors are supplied with positive voltage pulses. The difference between the first voltage potential and the second voltage potential is sufficient to erase the ReRAM device in the ReRAM cell. If the ReRAM cell is unselected for erasing, the gate of the one of the series-connected select transistors having its drain connected to an electrode of the ReRAM device is supplied with a voltage potential insufficient to turn it on.
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公开(公告)号：US20210005256A1
公开(公告)日：2021-01-07
申请号：US16525546
申请日：2019-07-29
Applicant: Microchip Technology Inc.
Inventor： John L. McCollum , Fengliang Xue
IPC: G11C13/00
Abstract: A ReRAM memory cell includes a ReRAM element, a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, and an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell. The programming circuit path is separate from the erase circuit path.
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公开(公告)号：US20200327937A1
公开(公告)日：2020-10-15
申请号：US16405895
申请日：2019-05-07
Applicant: Microchip Technology Inc.
Inventor： Victor Nguyen , Fethi Dhaoui , John L. McCollum , Fengliang Xue
Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.
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公开(公告)号：US10910050B2
公开(公告)日：2021-02-02
申请号：US16405895
申请日：2019-05-07
Applicant: Microchip Technology Inc.
Inventor： Victor Nguyen , Fethi Dhaoui , John L. McCollum , Fengliang Xue
Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.
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